Crossbar switch with input/output buffers having multiplexed control inputs

• US 5,717,871 A
• Filed: 08/17/1995
• Issued: 02/10/1998
• Est. Priority Date: 08/17/1995
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: I-Cube, Inc.
• Inventors: Sathe, Shrikant, Dahlgren, Kent, Hsieh, Wen-Jai, Horng, Chi-Song, Wong, Chun Chiu Daniel, Chou, Gerchih
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/516,319
• Time in Patent Office: 908 Days
• Field of Search: 395/250, 395/312
• US Class Current: 710/317
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13141 Hunting for free outlet, circuit or channel
• CPC Class Codes: H04Q 2213/13214 Clock signals
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/1332 Logic circuits
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 3/68 Grouping or interlacing selector groups or stages

Abstract

An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller. Each port stores an internal port address and when the key address matches the port address, the port asserts an internal "KEY" signal. Each port may be configured to use the KEY signal selectively as either its tristate, clock enable, clock or direction control signal.

Claims

1. An apparatus for selectively routing data signals between first terminals in response to input routing control data, port configuration data and port addressing data, the apparatus comprising:

a plurality of second terminals, each second terminal corresponding to a separate one of said first terminals;

switch means, connected to said second terminals and receiving said input routing control data, for routing signals between pairs of said second terminals selected in accordance with said input routing control data; and

a plurality of ports,

each port receiving said input port addressing data,

each port comprising means for receiving and storing a separate portion of said configuration data, said separate portion including a tag address and selection control data,

each port including means asserting and deasserting a key control signal according to whether the received port addressing data matches said tag address,

each port comprising buffer means connected between a separate corresponding pair of said first and second terminals and buffering a data signal between said corresponding pair, a mode of operation of said buffer means being controlled by a buffer control signal referenced by said selection control data, and

each port comprising means for routing said key control signal to said buffer means as said buffer control signal when said key control signal is referenced by said selection control data.

2. The apparatus in accordance with claim 1 wherein said buffer means comprises a tristate buffer and wherein said buffer control signal controls a state of said tristate buffer.

3. The apparatus in accordance with claim 1 wherein said buffer means comprises data storage means for storing data conveyed by said data signal and wherein said buffer control signal controls when said data storage means stores said data conveyed by said one of said data signals.

4. The apparatus in accordance with claim 1 wherein said buffer means port comprises a bidirectional buffer and wherein said buffer control signal controls a direction in which said buffer buffers said data signal between the pair of first and second terminals to which said buffer means is connected.

5. An apparatus for selectively routing data signals between first terminals in response to input routing control data, port configuration data, port addressing data, and input control signals, the apparatus comprising:

a plurality of second terminals, each second terminal corresponding to a separate one of said first terminals;

switch means, connected to said second terminals and receiving said input routing control data, for routing signals between pairs of said second terminals selected in accordance with said input routing control data; and

a plurality of ports,

each port receiving said input port addressing data,

each port comprising means for receiving and storing a separate portion of said configuration data, said separate portion including a tag address and selection control data,

each port including means asserting and deasserting a key control signal according to whether the received port addressing data matches said tag address,

each port comprising buffer means connected between a separate corresponding pair of said first and second terminals and buffering a data signal between said corresponding pair, a mode of operation of said buffer means being controlled by a buffer control signal, and

each port comprising selection means receiving said input control signals, said key control signal, and said selection control data, for routing one signal of said key control signal and said input control signals to said buffer means as said buffer control signal, said selection means selecting said one signal in response to said selection control data.

6. The apparatus in accordance with claim 5 wherein said buffer means comprises a tristate buffer and wherein said buffer control signal controls a state of said tristate buffer.

7. The apparatus in accordance with claim 5 wherein said buffer means comprises data storage means for storing data conveyed by said data signal and wherein said buffer control signal controls when said data storage means stores said data conveyed by said one of said data signals.

8. The apparatus in accordance with claim 5 wherein said buffer means comprises a bidirectional buffer and wherein said buffer control signal controls a direction in which said buffer buffers said data signal between said pair of first and second terminals to which said buffer means is connected.

9. An apparatus for selectively routing data signals between first terminals in response to input routing control data, port configuration data and port addressing data, and input control signals, the apparatus comprising:

a plurality of second terminals, each second terminal corresponding to a separate one of said first terminals;

switch means, connected to said second terminals and receiving said input routing control data, for routing signals between pairs of said second terminals selected in accordance with said input routing control data; and

plurality of ports,

each port receiving said input port addressing data,

each port comprising means for receiving and storing a separate portion of said configuration data, said separate portion including a tag address and selection control data,

each port including means asserting and deasserting a key control signal according to whether the received port addressing data matches said tag address,

each port comprising buffer means connected between a separate corresponding pair of said first and second terminals and buffering a data signal between said corresponding pair, mode of operation of said buffer means being controlled by a plurality of control signals, and

each port comprising means receiving said input control signals, said key control signal, and said selection control data, for routing a selected portion of said key control signal and said input control signals to said buffer means as said plurality of buffer control signals, said selection means selecting said portion in response to said selection control data.

10. The apparatus in accordance with claim 9

wherein said buffer means comprises a tristate buffer,

wherein said one of said buffer controls signal controls a state of said tristate buffer,

wherein said buffer means also comprises data storage means for storing data conveyed by said data signal, and

wherein another of said buffer control signals controls when said data storage means stores said data conveyed by said one of said data signals.

11. The apparatus in accordance with claim 9

wherein said buffer means comprises a bidirectional buffer,

wherein one of said buffer control signals controls a direction in which said buffer buffers said data signal between said pair of first and second terminals to which said buffer means is connected,

wherein said buffer means also comprises data storage means for storing data conveyed by said data signal, and

wherein another of said buffer control signals controls when said data storage means stores said data conveyed by said one of said data signals.

12. An apparatus for selectively routing data signals between first terminals in response to input routing control data, port configuration data and port addressing data, and input control signals, the apparatus comprising:

a plurality of second terminals, each second terminal corresponding to a separate one of said first terminals;

switch means, connected to said second terminals and receiving said input routing control data, for routing signals between pairs of said second terminals selected in accordance with said input routing control data; and

a plurality of ports,

each port receiving said input port addressing data,

each port comprising means for receiving and storing a separate portion of said configuration data, said separate portion including selection control data,

each port comprising buffer means connected between a separate corresponding pair of said first and second terminals and buffering a data signal between said corresponding pair, modes of operation of said buffer means being controlled by a plurality of control signals, and

each port comprising means for routing a selected portion of said input control signals to said buffer means as said plurality of buffer control signals in response to the stored selection control data.

13. The apparatus in accordance with claim 12

wherein said buffer means comprises a tristate buffer,

wherein said one of said buffer controls signal controls a state of said tristate buffer,

wherein said buffer means also comprises data storage means for storing data conveyed by said data signal, and

wherein another of said buffer control signals controls when said data storage means stores said data conveyed by said one of said data signals.

14. The apparatus in accordance with claim 12

wherein said buffer means comprises a bidirectional buffer,

wherein one of said buffer control signals controls a direction in which said buffer buffers said one of said data signals between said pair of first and second terminals to which said buffer means is connected,

wherein said buffer means also comprises data storage means for storing data conveyed by said data signal, and

wherein another of said buffer control signals controls when said data storage means stores said data conveyed by said one of said data signals.

15. An apparatus for selectively routing data signals between first terminals in response to input routing control data, port configuration data and port addressing data, and input control signals, the apparatus comprising:

a plurality of second terminals, each second terminal corresponding to a separate one of said first terminals;

switch means, connected to said second terminals and receiving said input routing control data, for routing signals between pairs of said second terminals selected in accordance with said input routing control data; and

a plurality of ports,

each port receiving said input port addressing data,

each port comprising means for receiving and storing a separate portion of said configuration data, said separate portion including selection control data;

each port comprising buffer means connected between a separate corresponding pair of said first and second terminals and buffering one of said data signals between said corresponding pair, mode of operation of said buffer means being controlled by a buffer control signal, and

each port comprising selection means connected for receiving said input control signals and an input data signal arriving on another one of said first terminals for selecting one signal from among said input control signals and said input data signal and routing the selected one signal to said buffer means as said buffer control signal, the selection of said one signal being made in response to the stored selection control data.

16. A time division multiplexer, responsive to input routing data, to pulses of an input clock signal and to pulses of an input clock enable signal, for receiving first input data signals and producing in response thereto second output data signals, comprising:

means for producing a KEY count value;

a plurality of input ports, each input port receiving a separate one of said first input data signals and comprising

means for storing a first TAG value, receiving the KEY count and asserting a first control signal when the KEY count matches the first TAG value, and

means receiving said first input data signal for storing a first data value conveyed by said one first input data signal on each pulse of said input clock signal, and for producing a first output signal representing the stored first data value when said first control signal is asserted,

a plurality of output ports, each output port producing a separate one of said second output data signals and comprising

means for storing a second TAG value, receiving the KEY count and asserting a second control signal when the KEY count matches the second TAG value, and

means for receiving a second input data signal, for storing a second data value conveyed by said second input data signal on each pulse of said input clock signal, and for producing said one second output signal representing the stored second data value when said second control signal is asserted; and

switch means for receiving the first output signals produced by each of said input ports and routing it as a second input signal to at least one of said output ports selected in accordance with input routing data.