System for coordinating coherency of cache memories of multiple host computers of a distributed information system

• US 5,717,897 A
• Filed: 09/09/1996
• Issued: 02/10/1998
• Est. Priority Date: 09/09/1996
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: McCrory, Duane J.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Langjahr, David
• Application Number:
  US08/709,595
• Time in Patent Office: 519 Days
• Field of Search: 395/468, 395/608, 395/291, 395/471, 395/800
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0817 using directory methods

Abstract

Apparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host computer includes a host cache controller which maintains the state of the data stored in its associated memory and maintains communicating with a main memory controller for participating in the control of coordinated reading and writing of data between the host cache memories and the main storage memory. The system maintains cache coherency by the exchange of commands between the main memory controller and the hosts cache controllers each of which define the state of the blocks of data stored in the host cache memories.

Claims

1. A system for coordinating cache coherency in a distributed information system, comprising:

at least one main storage memory;

a plurality of host computers, each having a cache memory add a host cache controller;

a main memory controller connected between said at least one main storage memory and said plurality of host computers;

each said host cache controller providing the means for communicating with said main memory controller and for participating in the control of the coordinated reading and writing of blocks of data between said host cache memories and said at least one main storage memory.

2. The system of claim 1, wherein said main memory controller includes a directory for describing the global cache state of each of the blocks of data stored in said host cache memories.

3. The system of claim 1, wherein said main memory controller includes a global cache for storing blocks of data stored by one or more of said host cache memories.

4. The system of claim 1, wherein one of said plurality of host sends an Acquire Block Shared command to said main memory controller when said host computer desires shared access to a block of data stored in said main storage memory.

5. The system of claim 1, wherein one of said plurality of host cache controller sends an Acquire Block Exclusive command to said main memory controller when said host computer desires to modify a block of data stored in said main storage memory,

said block of data being marked invalid in said host cache memory by said host cache controller.

6. The system of claim 1, wherein one of said plurality of host computers sends a Mark Block Exclusive command to said main memory controller when said host computer desire to modify a block of data stored in said main storage memory, said block of data being marked in said host cache memory as one of shared or invalid or by said cache controller.

7. The system of claim 1, wherein one of said plurality of host computers sends a Mark Block Shared and Write command to said controller when said host computer desires to write a block of data to said main storage memory and maintain shared access to said block of data, said block of data being marked modified in said host cache memory by said cache controller.

8. The system of claim 1, wherein one of said plurality of host computers sends a Mark Block Shared command to said main memory controller when said host computer does not intend to modify a block of data stored in said main storage memory, said block of data being marked exclusive in said host cache memory by said cache controller.

9. The system of claim 1, wherein one of said plurality of host computers sends a Mark Block Invalid and Write command to said main memory controller when said host computer desire requires to write a block of data to said main storage memory and terminate access to said block of data, said block of data being marked modified in said host cache memory by said cache controller.

10. The system of claim 1, wherein one of said plurality of host computers sends a Mark Block Invalid command to said main memory controller when said host computer desires to terminate access to a block of data, said block of data being marked exclusive in said host cache memory by said cache controller.

11. The system of claim 1, wherein said main memory controller sends a Transition Block Shared command to one of said plurality of host computers when said main memory controller desires that said one of said plurality of host computer when said main memory desires that said one of said plurality of host cache controllers to mark a block of data shared in said host cache memory.

12. The system of claim 1, wherein said main memory controller sends a Transition Block Invalid command to one of said plurality of host computers when said main memory controller desires that said one of said plurality of host computers mark a block of data invalid in said host cache memory.

13. A distributed processing system having a plurality of independently operable host computers arranged to share a main memory and maintain data coherency in the system, comprising;

main memory means comprising at least one main storage medium,

a plurality of host computers each having an associated cache memory and a cache controller,

a main controller coupled to said main memory means and to each of each cache controllers for maintaining cache coherency in said distributed processing system,

said main controller having a directory for recording and maintaining the global status of data in all of said cache memories, and

said main controller querying said directory in response to a command from a cache controller of a host computer in order to maintain coherency of data in the cache memories of the other host computers.

14. A system as set forth in claim 13 wherein said main controller further includes a second level cache memory for maintaining blocks of data also stored in host cache memories for speeding up data transfer between host computers.

15. A system as set forth in claim 13 wherein said host computers cache controllers maintains cache coherency between host computers by defining its blocks of data in one of a plurality of states.

16. A system as set forth in claim 15 wherein said plurality of states comprises modified, exclusive, shared and invalid states.

17. A system as set forth in claim 13 wherein said main controller maintains cache coherency between main memory and cache memories by defining blocks of data in its directory in one of three states comprising exclusive, shared or invalid.

18. A method of maintaining cache coherence between a plurality of host computers in a distributed processing system each having a cache memory and access to a shared main memory, comprising the steps of:

coupling the main memory to a main memory controller,

coupling said main memory controller to a plurality of individual cache controllers,

coupling each of said cache controllers to a host computer of the typed adapted to serve clients requests,

providing in said main memory controller a global directory for maintaining the state of said cache memories,

defining the state of each of said cache memories in one of four states,

changing the state of a cache memory in said global directory in response to a cache controller request, and

subsequently changing the state of the plural cache memories in response to the same request.

19. The method as set forth in claim 18 wherein said main memory controller maintains a state of each block of memory in each of said cache memories in its directory and provides access to said main memory.

20. The method as set forth in claim 19 wherein said cache controllers each are capable of defining the state of a block of data in its own cache memory as being modified, and

blocking access to the same block of unmodified data in said main memory until the modified block of data is transferred into main memory from a cache memory.