Apparatus and methods for automatically controlling block writes

• US 5,717,904 A
• Filed: 10/13/1995
• Issued: 02/10/1998
• Est. Priority Date: 10/02/1995
• Status: Expired due to Term

• Current Assignee: Brooktree Broadband Holding, Inc. (Synaptics Incorporated)
• Original Assignee: Brooktree Corporation (Rockwell Automation, Inc.)
• Inventors: Asal, Michael D., Ehlers, Steven B.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/543,236
• Time in Patent Office: 851 Days
• Field of Search: 395/501-503, 395/509, 395/511, 395/513, 395/521, 395/525, 395/526, 395/432, 345/186, 345/189, 365/230.03, 365/230.05, 365/230.06, 365/230.08
• US Class Current: 345/543
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A system for processing a stream of data and automatically selecting a portion or all of the data stream for block writing to a memory. The memory is capable of storing data in response to a block write command and a normal write command. The system contains a first data register and a second data register having the same data width. The first data register accepts data from the data stream in accordance with the its data width. Data stored in the first data register is transferred to the second data register. The first data register is then loaded with a portion of the data stream which is contiguous to the data stored in the first data register prior to the transferring. The data in the first and the second data registers is then compared. If the data in the first and the second registers is the same, then the content of a data counter is increased by one. When the content of the data counter exceeds a predetermined value, the system executes a block write command.

Claims

1. A method for processing a stream of data and automatically selecting a portion or all of said stream of data for block writing to a memory, said memory capable of storing data responsive to a block write command and a normal write command, said method comprising the steps of:

transferring data stored in a first data register to a second data register, said first and said second data register having a predetermined width;

loading said first data register with a portion of said stream of data which is contiguous to said data stored in said first data register prior to said transferring step;

comparing data stored in said first and said second data registers;

incrementing a data count in a data counter when said data stored in said first and said second data registers are the same; and

generating a block write signal when said data count exceeds a first predetermined value.

2. The method of claim 1 further comprising the step of allocating a data row in a data FIFO having a plurality of rows, each data row containing a field for storing data in said second data register and a field for storing said data count.

3. The method of claim 2 further comprising the step of allocating a new data row to said data FIFO when said block write signal is generated subsequent to generating a normal write signal.

4. The method of claim 3 further comprising the steps of:

storing a start address in a start address register; and

storing a control count indicating the number of consecutive addresses needed to be generated in conjunction with writing of data into said memory, said control count being updated when said new data row is allocated.

5. The method of claim 4 further comprising the step of allocating a control row in a control FIFO having a plurality of rows, each control row containing a field for storing said start address and a field for storing said control count.

6. The method of claim 5 wherein said control row is allocated when the sum of said data count and said control count exceeds a predetermined value.

7. The method of claim 5 wherein said control row comprises a field for storing a state indicating one of said block write and said normal write operations.

8. The method of claim 1 wherein said memory comprises a color register containing a value used for block write, said method further comprising the steps of:

storing a value in a last color register which is the same as said value stored in said color register;

comparing contents of said last color register and said second data register; and

generating a block write signal when said content of said last color register is the same as the content of said second data register and when said data count exceeds a second predetermined value.

9. The method of claim 1 wherein said memory comprises a color register containing a value used for block write, said method further comprising the steps of:

storing a value in a last color register which is the same as said value stored in said color register;

comparing contents of said last color register and said second data register; and

generating a color write signal in addition to said block write signal when said content of said last color register is the not same as the content of said second data register and when said data count exceeds a second predetermined value.

10. A method for processing a stream of data and automatically selecting a portion or all of said stream of data for block writing to a VRAM, said VRAM capable of performing a block write, a normal write, and a color write operation, said VRAM comprising a color register containing a value used for block write, said method comprising the steps of:

transferring data stored in a first data register to a second data register, said first and said second data register having a predetermined width;

loading said first data register with a portion of said stream of data which is contiguous to said data stored in said first data register prior to said transferring step;

comparing data stored in said first and said second data registers;

incrementing a data count in a data counter when said data stored in said first and said second data registers are the same; and

allocating a data row in a data FIFO having a plurality of rows, each data row coming a field for storing data in said second data register and a field for storing said data count;

storing a start address in a start address register;

storing a control count indicating the number of consecutive addresses needs to be generated in conjunction with writing of data into said VRAM, said control count being updated when said data row is allocated;

allocating a control row in a control FIFO having a plurality of rows, each control row containing a field for storing said start address and a field for storing said control count;

storing a value in a last color register which is the same as said value stored in said color register;

comparing contents of said last color register and said second data register; and

generating a block write signal when said content of said last color register is the same as the content of said second data register and when said data count exceeds a first predetermined value; and

generating a color write signal in addition to said block write signal when said content of said last color register is the not same as the content of said second data register and when said data count exceeds a second predetermined value.

11. The method of claim 10 further comprising the step of allocating a new data row when data stored in said first and said second data registers are not the same.

12. The method of claim 10 further comprising the step of allocating a new data row wherein said field for storing data contains data to be stored in said color register.

13. The method of claim 10 further comprising the step of allocating a new data row when said block write signal is generated subsequent to a normal write signal.

14. The method of claim 10 further comprising the steps of:

forming a sum of said data count and said control count; and

allocating a new control row when said sum exceeds a predetermined value.

15. The method of claim 10 further comprising the step of allocating a new control row when said block write signal is generated subsequent to a normal write signal.

16. A system for processing a stream of data and automatically selecting a portion or all of said stream of data for block writing to a memory, said memory capable of performing a block write and a normal write operation, said system comprising:

a first data register having a predetermined length, said first data register including a circuit, in response to a clock signal, for loading consecutive bits of said predetermined length from said stream of data into said first data register and for outputting data stored therein prior to said loading;

a second data register having said predetermined length, said second data register being connected to said first data register for receiving data output from said first data register;

a first comparison circuit for generating a count increment signal when contents of said first and said second data registers are the same;

a data counter for storing a data count, said data count being incremented in response to said count increment signal; and

a selection circuit for generating a block write signal when said data count exceeds a first predetermined value.

17. The system of claim 16 wherein said memory includes a color register containing a value used for block write, said system further comprising:

a last color register for storing a value which is the same as said value in said color register;

a second comparison circuit for comparing contents of said last color register and said second data register; and

wherein said selection circuit generates a color write signal for writing to said color register in addition to generating said block write signal when the content of said last color register is not the same as the content of said second data register and when said data count exceeds a second predetermined value.

18. The system of claim 16 wherein said memory contains a color register containing a value used for block write, said system further comprising:

a last color register for storing a value in said color register;

a second comparison circuit for comparing contents of said last color register and said second data register; and

wherein said selection circuit generates a block write signal when said content of said last color register is the same as the content of said second data register and when said data count exceeds a second predetermined value.

19. The system of claim 16 further comprising a data FIFO having a plurality of data rows, each data row containing a field for storing data in said second data register and a field for storing said data count.

20. The system of claim 19 further comprising means for allocating a new data row to said data FIFO when said selection circuit generates said block write signal subsequent to generating a normal write signal.

22. The system of claim 19 further comprising:

a start address register for storing a start address;

a control counter for storing a control count indicating the number of consecutive addresses needed to be generated in conjunction with writing of data into said memory, said control counter being updated when a new data row is allocated.

23. The system of claim 22 further comprising a control FIFO having a plurality of control rows, each control row containing a field for storing said start address and a field for storing said control count.

24. The control row of claim 23 further comprising a field for storing a state indicating one of said block write and said normal write operations.

25. The system of claim 16 further comprising:

a data FIFO having a plurality of data rows, each data row containing a field for storing data in said second data register and a field for storing said data count

a start address register for storing a start address;

a control counter for storing a control count indicating the number of consecutive addresses needed to be generated in conjunction with writing of data into said memory, said control counter being updated when a new data row is allocated;

a control FIFO having a plurality of control rows, each control row containing a field for storing said start address and a field for storing said control count.

a driver for retrieving said data row from said data FIFO and said control row from said control FIFO and for writing said data to said memory in accordance with said data count, said control count, and said block write signal.

21. The system of a new data rather comprising means for allocating a new data row to said data FIFO when said selection circuit generates said block write signal subsequent to generating a color write signal.

26. A system for processing a stream of data and automatically selecting a portion or all of said stream of data for block writing to a VRAM, said VRAM capable of performing a block write, a normal write, and a color write operation, said VRAM containing a color register having a value used for said block write operation, said system comprising:

a first data register having a predetermined length, said first data register including a circuit, in response to a clock signal, for loading consecutive bits of said predetermined length from said stream of data into said first data register and for outputting data stored therein prior to said loading;

a second data register having said predetermined length, said second data register being connected to said first data register for receiving data output from said first data register;

a first comparison circuit for generating a count increment signal when contents of said first and said second data registers are the same;

a data counter for storing a data count, said data count being incremented in response to said count increment signal;

a last color register for storing a value which is the same as said value in said color register;

a second comparison circuit for comparing contents of said last color register and said second data register; and

a selection circuit generating a color write signal and a block write signal when the content of said last color register is not the same as the content of said second data register and when said data count exceeds said first predetermined value, said selection circuit generating said block write signal when said content of said last color register is the same as the content of said second data register and when said count exceeds a second predetermined value.

27. The system of claim 26 further comprising:

a data FIFO having a plurality of data rows, each data row containing a field for storing data in said second data register and a field for storing said data count;

means for allocating a new data row to said data FIFO when said selection circuit generates said block write signal subsequent to generating a color write signal;

a start address register for storing a start address;

a control counter for storing a control count indicating the number of consecutive addresses needs to be generated in conjunction with writing of data into said VRAM, said control counter being updated when a new data row is allocated;

a control FIFO having a plurality of control rows, each control row containing a field for storing said start address, a field for storing said control count, and a field for storing a state indicating one of said block write, normal write, and color write operations; and

a driver for retrieving said data row from said data FIFO and said control row from said control FIFO and for writing said data to said VRAM in accordance with said data count, said control count, and said block write signal.

28. An automatic block write circuit for a multimedia system in a multimedia system with a shared bus for storing a stream of video, graphics and audio in a display memory, the display memory capable of storing the stream of data in a first number of memory locations in response to a first command, and capable of storing the stream of data in a second number of memory locations in response to a second command, the automatic block write circuit comprising:

a first data register having a predetermined length, said first data register including a circuit, in response to a clock signal, for loading consecutive bits of said predetermined length from said stream of data into said first data register and for outputting data stored therein prior to said loading;

a second data register having said predetermined length, said second data register being connected to said first data register for receiving data output from said first data register;

a first comparison circuit for generating a count increment signal when contents of said first and said second data registers are the same;

a data counter for storing a data count, said data count being incremented in response to said count increment signal; and

a selection circuit for generating a signal for storing in the second number of memory locations when said data count exceeds a first predetermined value;

whereby traffic on the shared bus is reduced.