Advanced parallel array processor (APAP)
First Claim
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1. A computer system, comprising:
- a plurality of processor memory elements on a common substrate each of said processor memory elements having internal and external communications paths for communication between a plurality of other processor memory elements on the substrate and for communication with other processing elements external to said substrate;
wherein the computer system provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including said plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.
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Abstract
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.
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Citations
117 Claims
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1. A computer system, comprising:
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a plurality of processor memory elements on a common substrate each of said processor memory elements having internal and external communications paths for communication between a plurality of other processor memory elements on the substrate and for communication with other processing elements external to said substrate; wherein the computer system provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including said plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112)
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113. A multi-processor memory system comprising:
- on a chip a plurality of processing elements with a network interface, said processing elements of said chip being intercoupled by an internal communication network for passing information between processing elements on the chip, and having a broadcast port for external communication from the chip, said processing elements on the chip have their own memory and they are coupled in a network as a torus, said system having a plurality of chips which are coupled chip to chip to form a parallel array of multiple nodes of chips, each node having a broadcast and control interface for communications between processing elements on a chip and between nodes.
- View Dependent Claims (114, 115)
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116. A computer system, comprising a plurality of chips which are coupled to form a parallel array of multiple nodes, each node having a broadcast and control interface for communications between processing elements on a chip and between nodes, said nodes being coupled by a network which is hypercube, selection means for selection of coupling paths to nodes in said modified hypercube network of nodes to change a path of coupled nodes in the network for the purpose of loading a node in parallel;
wherein the computer system provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.
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117. A parallel array computer system, comprising:
- a plurality of processing elements each having accessible memory and organized as cluster of processing elements, each of said processing elements of a cluster having a fast I/O tri-state driver;
wherein the parallel array computer system provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.
- a plurality of processing elements each having accessible memory and organized as cluster of processing elements, each of said processing elements of a cluster having a fast I/O tri-state driver;
Specification