Data processing system and method thereof
First Claim
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1. An integrated circuit, comprising:
- a vector engine capable of executing a vector instruction;
a scalar engine capable of executing a scalar instruction;
a sequencer for controlling execution of both the vector instruction in the vector engine and the scalar instruction in the scalar engine, the sequencer being coupled to the vector engine for communicating vector control information, the sequencer being coupled to the scalar engine for communicating scalar control information; and
a shared memory circuit for storing a vector operand and a scalar operand, the shared memory circuit being coupled to the vector engine for communicating the vector operand, the shared memory circuit being coupled to the scalar engine for communicating the scalar operand;
wherein the vector engine comprises;
a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;
a plurality of vector registers for storing a plurality of data values, each of the plurality of data values being selectively used during execution of the vector instruction; and
an arithmetic logic unit for executing arithmetic and logical operations, the arithmetic logic unit being coupled to each of the plurality of vector registers and to the shared memory circuit.
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Abstract
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.
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Citations
54 Claims
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1. An integrated circuit, comprising:
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a vector engine capable of executing a vector instruction; a scalar engine capable of executing a scalar instruction; a sequencer for controlling execution of both the vector instruction in the vector engine and the scalar instruction in the scalar engine, the sequencer being coupled to the vector engine for communicating vector control information, the sequencer being coupled to the scalar engine for communicating scalar control information; and a shared memory circuit for storing a vector operand and a scalar operand, the shared memory circuit being coupled to the vector engine for communicating the vector operand, the shared memory circuit being coupled to the scalar engine for communicating the scalar operand; wherein the vector engine comprises; a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising; a plurality of vector registers for storing a plurality of data values, each of the plurality of data values being selectively used during execution of the vector instruction; and an arithmetic logic unit for executing arithmetic and logical operations, the arithmetic logic unit being coupled to each of the plurality of vector registers and to the shared memory circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An integrated circuit, comprising:
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an instruction memory for storing a plurality of instructions, each of the plurality of instructions being one of a vector instruction and a scalar instruction; a vector engine capable of executing a vector operation in response to the vector instruction; a scalar engine capable of executing a scalar operation in response to the scalar instruction; a sequencer for controlling execution of both the vector operation in the vector engine and the scalar operation in the scalar engine, the sequencer being coupled to the vector engine for communicating vector control information, the sequencer being coupled to the scalar engine for communicating scalar information, the sequencer being coupled to the instruction memory for receiving a first one of the plurality of instructions; a shared memory circuit for storing a plurality of operands, each of the plurality of operands being used during execution of one of the vector and scalar operations, the shared memory circuit being coupled to the vector engine for communicating a first one of the plurality of operands, the shared memory circuit being coupled to the scalar engine for communicating a second one of the plurality of operands; an input data register coupled to the vector engine, the input data register storing a plurality of data values; and a programmable integrated circuit pin, the programmable integrated circuit pin being programmed as one of an input integrated circuit pin and an output integrated circuit pin. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 54)
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30. A data processor, comprising:
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a vector engine capable of executing a vector operation in response to a vector instruction; a scalar engine capable of executing a scalar operation in response to a scalar instruction; a first bus portion, coupled to said vector engine, for providing the vector instruction to said vector engine; a second bus portion, coupled to said scalar engine, for providing the scalar instruction to said scalar engine; and interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine; wherein the vector engine comprises; a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising; vector control circuitry for controlling operation of that one of the plurality of processing elements; a first vector register bit field storage circuit for storing a portion of a vector data value, the portion of the vector data value being selectively used during execution of the vector instruction; a second vector register bit field storage circuit for storing a vector control value, at least a portion of the vector control value being used to enable operation of that one of the plurality of processing elements during execution of the vector instruction, said second vector register bit field storage circuit being coupled to said vector control circuitry; and a vector arithmetic/logic unit for executing at least one of an arithmetic operation and a logical operation, said vector arithmetic/logic unit being coupled to said first vector register bit field storage circuit and to said vector control circuitry; and wherein the scalar engine comprises; a scalar execution unit for executing the scalar instruction, said scalar execution unit comprising; scalar control circuitry for controlling operation of said scalar execution unit; a first scalar register bit field storage circuit for storing a scalar data value, at least a portion of the scalar data value being selectively used during execution of the scalar instruction; a second scalar register bit field storage circuit for storing a scalar control value, at least a portion of the scalar control value being used during execution of the scalar instruction, said second scalar register bit field storage circuit being coupled to said scalar control circuitry; and a scalar arithmetic/logic unit for executing at least one of an arithmetic operation and a logical operation, said scalar arithmetic/logic unit being coupled to said first scalar register bit field storage circuit and to said scalar control circuitry. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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37. A data processor, comprising:
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a vector engine capable of executing a vector operation on a vector value in response to a vector instruction; a vector memory array coupled to said vector engine for providing the vector value to said vector engine; a scalar engine capable of executing a scalar operation on a scalar value in response to a scalar instruction; a scalar memory coupled to said scalar engine for providing the scalar value to said scalar engine; an instruction memory for storing at least the vector instruction and the scalar instruction, for providing the vector instruction to said vector engine, and for providing the scalar instruction to said scalar engine; and interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine; wherein the vector engine comprises; a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising; vector control circuitry for controlling operation of that one of the plurality of processing elements during execution of the vector instruction; at least one vector register, coupled to said vector control circuitry; and vector computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the vector instruction, said vector computational logic being coupled to said vector control circuitry; and wherein the scalar engine comprises; scalar control circuitry for controlling operation of said scalar engine during execution of the scalar instruction; at least one scalar register, coupled to said scalar control circuitry; and scalar computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the scalar instruction, said scalar computational logic being coupled to said scalar control circuitry. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A data processor, comprising:
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a vector engine capable of executing a vector instruction; a scalar engine capable of executing a scalar instruction; instruction receiving circuitry for providing the vector instruction to said vector engine and for providing the scalar instruction to said scalar engine; and interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine; wherein the vector engine comprises; a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising; vector control circuitry for controlling operation of that one of the plurality of processing elements during execution of the vector instruction; at least one vector register, coupled to said vector control circuitry; and vector computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the vector instruction, said vector computational logic being coupled to said vector control circuitry; and wherein the scalar engine comprises; scalar control circuitry for controlling operation of said scalar engine during execution of the scalar instruction; at least one scalar register, coupled to said scalar control circuitry; and scalar computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the scalar instruction, said scalar computational logic being coupled to said scalar control circuitry. - View Dependent Claims (50, 51, 52, 53)
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Specification