Data processing system and method thereof

• US 5,717,947 A
• Filed: 03/31/1993
• Issued: 02/10/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Osborn, Stephen G., Tomazin, Thomas J., Lawell, Terry G., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/040,779
• Time in Patent Office: 1,777 Days
• Field of Search: 395/800, 395/375, 395/325, 395/800.03, 395/800.02, 395/800.07, 395/800.09, 395/800.11, 395/800.22, 395/800.16, 395/379, 395/309, 395/310
• US Class Current: 712/3
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. An integrated circuit, comprising:

a vector engine capable of executing a vector instruction;

a scalar engine capable of executing a scalar instruction;

a sequencer for controlling execution of both the vector instruction in the vector engine and the scalar instruction in the scalar engine, the sequencer being coupled to the vector engine for communicating vector control information, the sequencer being coupled to the scalar engine for communicating scalar control information; and

a shared memory circuit for storing a vector operand and a scalar operand, the shared memory circuit being coupled to the vector engine for communicating the vector operand, the shared memory circuit being coupled to the scalar engine for communicating the scalar operand;

wherein the vector engine comprises;

a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;

a plurality of vector registers for storing a plurality of data values, each of the plurality of data values being selectively used during execution of the vector instruction; and

an arithmetic logic unit for executing arithmetic and logical operations, the arithmetic logic unit being coupled to each of the plurality of vector registers and to the shared memory circuit.

2. The integrated circuit of claim 1 wherein the sequencer controls execution of the vector instruction and the scalar instruction non-concurrently.

3. The integrated circuit of claim 1 further comprising:

an instruction storage circuit, coupled to said sequencer.

4. The integrated circuit of claim 1 wherein each one of the plurality of processing elements corresponds to a portion of the shared memory circuit.

5. The integrated circuit of claim 1 further comprising:

an input data register coupled to the vector engine, the input data register storing a plurality of data values.

6. The integrated circuit of claim 1 wherein the scalar engine comprises:

a plurality of scalar pointer registers, each of the plurality of scalar pointer registers storing one of a scalar pointer address value and a first scalar data value; and

a plurality of scalar data registers, each of the plurality of scalar data registers storing a second scalar data value.

7. The integrated circuit of claim 6 wherein the scalar pointer address value stored in each of the plurality of scalar pointer registers indicates one of an address of the vector operand in the shared memory circuit and an address of a scalar value stored in an input data register.

8. The integrated circuit of claim 7 wherein the address of the vector operand in the shared memory circuit indicates a column of memory storage locations in the shared memory circuit.

9. The integrated circuit of claim 6 wherein the scalar pointer address value stored in one of the plurality of scalar pointer registers indicates one of a plurality of processing elements in the vector engine.

10. The integrated circuit of claim 6 wherein the scalar engine further comprises:

an arithmetic logic unit for executing arithmetic and logical operations, the arithmetic logic unit being coupled to each of the plurality of scalar data registers, each of the plurality of scalar pointer registers, and to the shared memory circuit.

11. The integrated circuit of claim 5 wherein the input data register provides at least one of the plurality of data values stored therein to the vector engine in response to one of a first and a second access mode of the vector instruction.

12. The integrated circuit of claim 11 wherein the first access mode enables the input data register to provide one of the plurality of data values to the vector engine, the one of the plurality of data values being provided to each of the plurality of processing elements in the vector engine.

13. The integrated circuit of claim 11 wherein the second access mode enables the input data register to provide a plurality of data values to the vector engine, each one of the plurality of data values being provided to one of the plurality of processing elements of the vector engine.

14. The integrated circuit of claim 1 further comprising a plurality of integrated circuit pins which indicates internal state information of the integrated circuit.

15. The integrated circuit of claim 14 wherein the plurality of integrated circuit pins provides a plurality of status signals which collectively indicates an instruction state of the integrated circuit, the instruction state indicating one of:

when a stall instruction is being executed;

when a write instruction is being executed;

when the vector instruction is being executed;

when the scalar instruction is being executed;

when a conditional instruction is being executed;

when an exception has occurred during execution of one of the vector instruction and the scalar instruction;

when a branch instruction results in execution of a branch operation; and

when a branch instruction does not result in execution of the branch operation.

16. The integrated circuit of claim 1 further comprising a programmable integrated circuit pin, the programmable integrated circuit pin being programmed as one of an input integrated circuit pin and an output integrated circuit pin.

17. An integrated circuit, comprising:

an instruction memory for storing a plurality of instructions, each of the plurality of instructions being one of a vector instruction and a scalar instruction;

a vector engine capable of executing a vector operation in response to the vector instruction;

a scalar engine capable of executing a scalar operation in response to the scalar instruction;

a sequencer for controlling execution of both the vector operation in the vector engine and the scalar operation in the scalar engine, the sequencer being coupled to the vector engine for communicating vector control information, the sequencer being coupled to the scalar engine for communicating scalar information, the sequencer being coupled to the instruction memory for receiving a first one of the plurality of instructions;

a shared memory circuit for storing a plurality of operands, each of the plurality of operands being used during execution of one of the vector and scalar operations, the shared memory circuit being coupled to the vector engine for communicating a first one of the plurality of operands, the shared memory circuit being coupled to the scalar engine for communicating a second one of the plurality of operands;

an input data register coupled to the vector engine, the input data register storing a plurality of data values; and

a programmable integrated circuit pin, the programmable integrated circuit pin being programmed as one of an input integrated circuit pin and an output integrated circuit pin.

18. The integrated circuit of claim 17 further comprising:

a first port for communicating digital data;

a second port for communicating digital data;

a third port for communicating digital data;

a fourth port for communicating digital data;

a control register for storing a control value;

a first switch circuit coupled between the first port and the second port, the first switch circuit being in one of a conducting mode and a non-conducting mode in response to a first portion of the control value, wherein when the first switch is in the conducting mode, digital data is transferred between the first port and the second port and when the first switch is in the non-conducting mode, no digital data is transferred between the first port and the second port;

a second switch circuit coupled between the third port and the fourth port, the second switch circuit being in one of a conducting mode and a non-conducting mode in response to a second portion of the control value, wherein when the second switch is in the conducting mode, digital data is transferred between the third port and the fourth port and when the second switch is in the non-conducting mode, no digital data is transferred between the third port and the fourth port;

a first tap circuit coupled between the first port and the input data register, the first tap circuit being in one of the conducting mode and the non-conducting mode in response to a third portion of the control value, wherein when the first tap is in the conducting mode, digital data is transferred from the first port to the input data register and when the first tap is in the non-conducting mode, no digital data is transferred from the first port to the input data register;

a second tap circuit coupled between the second port and the input data register, the first tap circuit being in one of the conducting mode and the non-conducting mode in response to a fourth portion of the control value, wherein when the second tap is in the conducting mode, digital data is transferred from the second port to the input data register and when the second tap is in the non-conducting mode, no digital data is transferred from the second port to the input data register;

a third tap circuit coupled between the third port and the input data register, the third tap circuit being in one of the conducting mode and the non-conducting mode in response to a fifth portion of the control value, wherein when the third tap is in the conducting mode, digital data is transferred from the third port to the input data register and when the third tap is in the non-conducting mode, no digital data is transferred from the third port to the input data register; and

a fourth tap circuit coupled between the fourth port and the input data register, the fourth tap circuit being in one of the conducting mode and the non-conducting mode in response to a sixth portion of the control value, wherein when the fourth tap is in the conducting mode, digital data is transferred from the fourth port to the input data register and when the fourth tap is in the non-conducting mode, no digital data is transferred from the fourth port to the input data register.

19. The integrated circuit of claim 17 wherein the sequencer controls execution of the vector instruction and the scalar instruction non-concurrently.

20. The integrated circuit of claim 17 wherein the scalar engine comprises:

a plurality of scalar pointer registers, each of the plurality of scalar pointer registers storing one of a scalar pointer address value and a first scalar data value; and

a plurality of scalar data registers, each of the plurality of scalar data registers storing a second scalar data value.

21. The integrated circuit of claim 20 wherein the scalar pointer address value stored in each of the plurality of scalar pointer registers indicates one of an address of the vector operand in the shared memory circuit and an address of a scalar value stored in an input data register.

22. The integrated circuit of claim 20 wherein the scalar engine further comprises:

an arithmetic logic unit for executing arithmetic and logical operations, the arithmetic logic unit being coupled to each of the plurality of scalar data registers, each of the plurality of scalar pointer registers, and to the shared memory circuit.

23. The integrated circuit of claim 17 wherein the vector engine comprises:

a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;

a plurality of vector registers for storing a plurality of data values, each of the plurality of data values being selectively used during execution of the vector instruction; and

an arithmetic logic unit for executing arithmetic and logical operations, the arithmetic logic unit being coupled to each of the plurality of vector registers and to the shared memory circuit.

24. The integrated circuit of claim 23 wherein each one of the plurality of processing elements corresponds to a row of a plurality of memory storage elements of the shared memory circuit.

25. The integrated circuit of claim 17 wherein the input data register provides at least one of the plurality of data values stored therein to the vector engine in response to one of a first and a second access mode of the vector instruction.

26. The integrated circuit of claim 25 wherein the second access mode enables the input data register to provide a plurality of data values to the vector engine, each one of the plurality of data values being provided to one of the plurality of processing elements of the vector engine.

27. The integrated circuit of claim 17 further comprising a plurality of integrated circuit pins which indicates internal state information of the integrated circuit.

28. The integrated circuit of claim 27 wherein the plurality of integrated circuit pins provides a plurality of status signals which collectively indicates an instruction state of the integrated circuit, the instruction state indicating one of:

when a stall operation is being executed;

when a write instruction is being executed;

when the vector instruction is being executed;

when the scalar instruction is being executed;

when a conditional instruction is being executed;

when an exception has occurred during execution of one of the vector instruction and the scalar instruction;

when a branch instruction results in execution of a branch operation; and

when a branch instruction does not result in execution of the branch operation.

29. The integrated circuit of claim 17 further comprising stall circuitry for stalling one of said vector engine and said scalar engine.

54. The integrated circuit of claim 25 wherein the first access mode enables the input data register to provide one of the plurality of data values to the vector engine, the one of the plurality of data values being provided to each of the plurality of processing elements in the vector engine.

30. A data processor, comprising:

a vector engine capable of executing a vector operation in response to a vector instruction;

a scalar engine capable of executing a scalar operation in response to a scalar instruction;

a first bus portion, coupled to said vector engine, for providing the vector instruction to said vector engine;

a second bus portion, coupled to said scalar engine, for providing the scalar instruction to said scalar engine; and

interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine;

wherein the vector engine comprises;

a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;

vector control circuitry for controlling operation of that one of the plurality of processing elements;

a first vector register bit field storage circuit for storing a portion of a vector data value, the portion of the vector data value being selectively used during execution of the vector instruction;

a second vector register bit field storage circuit for storing a vector control value, at least a portion of the vector control value being used to enable operation of that one of the plurality of processing elements during execution of the vector instruction, said second vector register bit field storage circuit being coupled to said vector control circuitry; and

a vector arithmetic/logic unit for executing at least one of an arithmetic operation and a logical operation, said vector arithmetic/logic unit being coupled to said first vector register bit field storage circuit and to said vector control circuitry; and

wherein the scalar engine comprises;

a scalar execution unit for executing the scalar instruction, said scalar execution unit comprising;

scalar control circuitry for controlling operation of said scalar execution unit;

a first scalar register bit field storage circuit for storing a scalar data value, at least a portion of the scalar data value being selectively used during execution of the scalar instruction;

a second scalar register bit field storage circuit for storing a scalar control value, at least a portion of the scalar control value being used during execution of the scalar instruction, said second scalar register bit field storage circuit being coupled to said scalar control circuitry; and

a scalar arithmetic/logic unit for executing at least one of an arithmetic operation and a logical operation, said scalar arithmetic/logic unit being coupled to said first scalar register bit field storage circuit and to said scalar control circuitry.

31. A data processor as in claim 30, further comprising:

an instruction cache, coupled to the first bus portion, for storing the vector instruction.

32. A data processor as in claim 31, wherein said instruction cache is coupled to said second bus portion and wherein said instruction cache stores the scalar instruction.

33. A data processor as in claim 30, wherein said data processor is formed on a single integrated circuit.

34. A data processor as in claim 33, further comprising:

external interface circuitry, coupled to said vector engine for providing information external to the single integrated circuit from said vector engine, and coupled to said scalar engine for providing information external to the single integrated circuit from said scalar engine.

35. A data processor as in claim 30, further comprising:

a memory array, coupled to said vector engine, for storing a plurality of vectors to be used by said vector engine during execution of a second vector instruction.

36. A data processor as in claim 35, wherein said memory array is coupled to said scalar engine and stores a plurality of scalars to be used during execution of a second scalar instruction.

37. A data processor, comprising:

a vector engine capable of executing a vector operation on a vector value in response to a vector instruction;

a vector memory array coupled to said vector engine for providing the vector value to said vector engine;

a scalar engine capable of executing a scalar operation on a scalar value in response to a scalar instruction;

a scalar memory coupled to said scalar engine for providing the scalar value to said scalar engine;

an instruction memory for storing at least the vector instruction and the scalar instruction, for providing the vector instruction to said vector engine, and for providing the scalar instruction to said scalar engine; and

interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine;

wherein the vector engine comprises;

a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;

vector control circuitry for controlling operation of that one of the plurality of processing elements during execution of the vector instruction;

at least one vector register, coupled to said vector control circuitry; and

vector computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the vector instruction, said vector computational logic being coupled to said vector control circuitry; and

wherein the scalar engine comprises;

scalar control circuitry for controlling operation of said scalar engine during execution of the scalar instruction;

at least one scalar register, coupled to said scalar control circuitry; and

scalar computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the scalar instruction, said scalar computational logic being coupled to said scalar control circuitry.

38. A data processor as in claim 37, further comprising:

external interface circuitry, coupled to said vector memory array and to said scalar memory, said external interface circuitry providing external access to said vector memory array and to said scalar memory.

39. A data processor as in claim 38, wherein said external interface circuitry provides the vector value to said vector memory array before said vector engine begins executing said vector instruction, and wherein said external interface circuitry provides a second vector value to said vector memory array concurrent with said vector engine executing said vector instruction.

40. A data processor as in claim 38, wherein operation of said external interface circuitry is controlled by a plurality of control values provided by said scalar engine.

41. A data processor as in claim 40, wherein the plurality of control values are user programmable and are stored in at least one scalar register.

42. A data processor as in claim 38, wherein said instruction memory includes a vector instruction cache portion for storing the vector instruction and a scalar instruction cache portion for storing the scalar instruction.

43. A data processor as in claim 37, wherein said data processor is formed on a single integrated circuit.

44. A data processor as in claim 43, wherein said vector instruction is executed by said plurality of processing elements concurrently.

45. A data processor as in claim 37, wherein said at least one vector register in each one of the plurality of processing elements stores status information for that one of the plurality of processing elements.

46. A data processor as in claim 37, wherein said at least one vector register in each one of the plurality of processing elements comprises a plurality of vector registers, and wherein the plurality of vector registers store control and status information for that one of the plurality of processing elements.

47. A data processor as in claim 37, wherein said at least one vector register in each one of the plurality of processing elements comprises a plurality of vector registers, and wherein the plurality of vector registers store data as well as control and status information for that one of the plurality of processing elements.

48. A data processor as in claim 37, wherein during execution of the vector instruction, data is transferred between at least two of the plurality of processing elements under control of the vector control circuitry in the at least two of the plurality of processing elements.

49. A data processor, comprising:

a vector engine capable of executing a vector instruction;

a scalar engine capable of executing a scalar instruction;

instruction receiving circuitry for providing the vector instruction to said vector engine and for providing the scalar instruction to said scalar engine; and

interface circuitry, coupled to said vector engine and to said scalar engine, said interface circuitry providing coordination between said vector engine and said scalar engine;

wherein the vector engine comprises;

a plurality of processing elements for executing the vector instruction, each one of the plurality of processing elements comprising;

vector control circuitry for controlling operation of that one of the plurality of processing elements during execution of the vector instruction;

at least one vector register, coupled to said vector control circuitry; and

vector computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the vector instruction, said vector computational logic being coupled to said vector control circuitry; and

wherein the scalar engine comprises;

scalar control circuitry for controlling operation of said scalar engine during execution of the scalar instruction;

at least one scalar register, coupled to said scalar control circuitry; and

scalar computational logic for performing at least one of an arithmetic operation and a logical operation during execution of the scalar instruction, said scalar computational logic being coupled to said scalar control circuitry.

50. A data processor as in claim 49, wherein said data processor is formed on a single integrated circuit.

51. A data processor as in claim 50, further comprising:

external interface circuitry, coupled to said vector engine for providing information external to the single integrated circuit from said vector engine, and coupled to said scalar engine for providing information external to the single integrated circuit from said scalar engine.

52. A data processor as in claim 49, further comprising:

an instruction cache, coupled to the instruction receiving circuitry, for storing the vector instruction and the scalar instruction.

53. A data processor as in claim 49, further comprising:

a memory array, coupled to said vector engine and to said scalar engine, said memory array storing a plurality of vectors to be used by said vector engine during execution of the vector instruction, and said memory array storing at least one scalar to be used by said scalar engine during execution of the scalar instruction.