Three-terminal MOS-gate controlled thyristor structures with current saturation characteristics

• US 5,719,411 A
• Filed: 08/18/1995
• Issued: 02/17/1998
• Est. Priority Date: 07/28/1994
• Status: Expired due to Fees

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ajit, Janardhanan S.
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/516,824
• Time in Patent Office: 914 Days
• Field of Search: 257/132, 257/133, 257/137, 257/138, 257/146, 257/154, 257/163
• US Class Current: 257/132
• CPC Class Codes: H01L 29/7412 the device being a diode
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

MOS-gate controlled thyristor structures which have current saturation characteristics, do not have any parasitic thyristor structure, and require only a single gate drive. A resistive structure such as a MOSFET, Schottky diode, PN junction diode, diffused resistor or punch-through device (e.g. punch through PNP structure) is incorporated in series with the N⁺ emitter of the thyristor. In the on-state of the device, with a positive gate voltage, when operating at high currents, because of the voltage drop in the resistive structure in series with the N⁺ emitter, the potential of the N⁺ emitter, and along with it the potential of the P base, increases. When the potential is increased beyond a certain predetermined value, diversion of current is accomplished by one of the following ways: (i) the smallest distance between the P base region and the P⁺ cathode is such that punch-through occurs in these regions. Occurrence of punch-through creates paths to divert the hole current at areas where punch-through occurs; (ii) the threshold voltage and channel conductance of a PMOS is such that sufficient hole current diversion occurs. The doping of the P base region is such that formation of these punch-through or PMOS channel paths causes the resistance of the P base regions to ground to become sufficiently low so as to cause the thyristor current to become less than its holding current. This causes the thyristor to become unlatched. But the transistor paths (PNP and IGBT current paths) in the device still conduct current because the gate voltage of the turn-on DMOSFET is greater that its threshold voltage. Current in the device ultimately saturates similar to an IGBT.

Claims

1. A MOS-controlled thyristor, comprising:

a wafer of semiconductor material having first and second spaced, parallel planar surfaces, at least a portion of the thickness of the wafer which extends from said first semiconductor surface comprising a relatively lightly doped layer of a first conductivity type for receiving junctions, at least a portion of the thickness of said wafer which extends from said second semiconductor surface comprising a relatively highly doped layer of a second conductivity type;

a first region of said second conductivity type comprising a base region formed in said relatively lightly doped layer of said first conductivity type and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface;

an emitter region of said first conductivity type formed in said base and extending from said first semiconductor surface to a second depth beneath said semiconductor surface which is shallower than said first depth to create an emitter/base junction, said emitter region being radially inwardly spaced along said first semiconductor surface along edges of said base, such that said edges of said base extend to said first semiconductor surface, thereby defining a first channel region along a first of said edges;

a second region of said second conductivity type comprising a cathode region formed in said relatively lightly doped layer of said first conductivity type and extending from said first semiconductor surface, said cathode region being laterally spaced from said first edge of said base to form a second channel region in said relatively lightly doped layer of said first conductivity type;

a resistive structure disposed in series with said emitter region, said resistive structure comprising at least one structure selected from the group consisting of a MOSFET, a punch-through device, a diffused resistance, an N⁺ contact resistance, a polysilicon resistive structure, a PN junction diode and a Shottky diode;

gate insulation layer means on said first semiconductor surface disposed at least on said first and second channel regions;

gate means disposed over said gate insulation layer means and overlying said first and second channel regions;

first electrode means connected to said layer of second conductivity type disposed on said second semiconductor surface;

second electrode means connected to said cathode region of second conductivity type, and

gate electrode means connected to said gate means.

2. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a MOSFET.

3. The MOS-controlled thyristor of claim 2, wherein said MOSFET comprises a PMOS transistor.

4. The MOS-controlled thyristor of claim 2, wherein said MOSFET comprises an NMOS transistor.

5. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a MOSFET and a punch-through device disposed in series with said emitter region.

6. The MOS-controlled thyristor of claim 5, wherein said MOSFET comprises a PMOS transistor and said punch-through device comprises a punch-through PNP transistor disposed in series with said emitter region.

7. The MOS-controlled thyristor of claim 5, wherein said MOSFET comprises an NMOS transistor and said punch-through device comprises a punch-through NPN transistor disposed in series with said emitter region.

8. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a diffused resistance disposed in series with said emitter region.

9. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a contact resistance disposed in series with said emitter region.

10. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a diffused resistance and a contact resistance disposed in series with said emitter region.

11. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a punch-through device disposed in series with said emitter region.

12. The MOS-controlled thyristor of claim 11, wherein said punch-through device comprises a punch-through PNP structure.

13. The MOS-controlled thyristor of claim 11, wherein said punch-through device comprises a punch-through NPN structure.

14. The MOS-controlled thyristor of claim 1, wherein said resistive device comprises a polysilicon resistive structure in series with said emitter.

15. The MOS-controlled thyristor of claim 1, further comprising a relatively lightly doped diffusion of said second conductivity type disposed under said gate electrode means between said base region and said cathode region.

16. The MOS-controlled thyristor of claim 1, wherein said thyristor is provided in a cellular topology.

17. The MOS-controlled thyristor of claim 1, further comprising a layer of said first conductivity type disposed between said layer of said second conductivity type and said relatively lightly doped layer of said first conductivity type.

18. The MOS-controlled thyristor of claim 1, wherein said emitter is relatively highly doped.

19. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a PN junction diode.

20. The MOS-controlled thyristor of claim 1, wherein said resistive structure comprises a Schottky diode.

21. The MOS-controlled thyristor of claim 14, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from base region to diverter region.

22. The MOS-controlled thyristor of claim 14, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from said base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of said first conductivity type extending between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

23. The MOS-controlled thyristor of claim 21, further comprising a relatively lightly doped diffusion of said second conductivity type disposed under said gate electrode means between said base region and said cathode region.

24. The MOS-controlled thyristor of claim 22, further comprising a relatively lightly doped diffusion of said second conductivity type disposed under said gate electrode means between said base region and said cathode region.

25. The MOS-controlled thyristor of claim 20, further comprising a diverter region of said second conductivity type contacted by second electrode spaced from said base region, such that said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

26. The MOS-controlled thyristor of claim 20, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of first conductivity type between the said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

27. The MOS-controlled thyristor of claim 25, further comprising a relatively lightly doped diffusion of second conductivity type disposed under said gate electrode means between said base region and said cathode region.

28. The MOS-controlled thyristor of claim 26, further comprising a relatively lightly doped diffusion of said second conductivity type disposed under said gate electrode means between said base region and said cathode region.

29. The MOS-controlled thyristor of claim 2, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from said base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

30. The MOS-controlled thyristor of claim 2, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from said base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of said first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

31. The MOS-controlled thyristor of claim 5, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from base region to diverter region.

32. The MOS-controlled thyristor of claim 5, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of said first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

33. The MOS-controlled thyristor of claim 8, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

34. The MOS-controlled thyristor of claim 8, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

35. The MOS-controlled thyristor of claim 9, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

36. The MOS-controlled thyristor of claim 9, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from said base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of said first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

37. The MOS-controlled thyristor of claim 10, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

38. The MOS-controlled thyristor of claim 10, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from said base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of said first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

39. The MOS-controlled thyristor of claim 11, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from said base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

40. The MOS-controlled thyristor of claim 11, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from said base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of said first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

41. The MOS-controlled thyristor of claim 19, further comprising a diverter region of said second conductivity type and a second electrode contacting said diverter region and spaced from base region, whereby said base region punches through to said diverter region when said base region reaches a predetermined potential, causing diversion of hole current from said base region to said diverter region.

42. The MOS-controlled thyristor of claim 19, further comprising a diverter region of said second conductivity type, a second electrode contacting said diverter region and spaced from said base region, and a second gate contacting said second electrode and overlying said relatively lightly doped layer of first conductivity type between said diverter region and said base region to form a MOSFET from said base region to said diverter region, said MOSFET being activated when the potential of said base region increases beyond a threshold voltage of said MOSFET, thereby causing diversion of hole current from said base region to said diverter region.

43. A MOS-controlled thyristor, comprising:

a wafer of semiconductor material having first and second spaced, parallel planar surfaces, at least a portion of the thickness of the wafer which extends from said first semiconductor surface comprising a relatively lightly doped layer of a first conductivity type for receiving junctions, at least a portion of the thickness of said wafer which extends from said second semiconductor surface comprising a relatively highly doped layer of a second conductivity type;

a first region of said second conductivity type comprising a base region formed in said relatively lightly doped layer of said first conductivity type and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface;

an emitter region of said first conductivity type formed in said base and extending from said first semiconductor surface to a second depth beneath said semiconductor surface which is shallower than said first depth to create an emitter/base junction, said emitter region being radially inwardly spaced along said first semiconductor surface along edges of said base, such that said edges of said base extend to said first semiconductor surface, thereby defining a first channel region along a first of said edges;

a second region of said second conductivity type comprising a cathode region formed in said relatively lightly doped layer of said first conductivity type and extending from said first semiconductor surface, said cathode region being laterally spaced from said first edge of said base region to form a second channel region in said relatively lightly doped layer of said first conductivity type;

resistive means disposed in series with said emitter region for creating a sufficient voltage drop between said emitter region and said base region when said thyristor is conducting current, such that the potential of said base region increases beyond a predetermined value where punch-through or hole diversion occurs between said base region and said cathode region;

gate insulation layer means on said first semiconductor surface disposed at least on said first and second channel regions;

gate means disposed over said gate insulation layer means and overlying said first and second channel regions;

first electrode means connected to said layer of second conductivity type disposed on said second semiconductor surface;

second electrode means connected to said cathode region of second conductivity type, and

gate electrode means connected to said gate means.