Multiple implant lightly doped drain (MILDD) field effect transistor

• US 5,719,425 A
• Filed: 01/31/1996
• Issued: 02/17/1998
• Est. Priority Date: 01/31/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Ditali, Akram
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/594,516
• Time in Patent Office: 748 Days
• Field of Search: 257/336, 257/337, 257/338, 257/344, 257/388, 257/408, 257/900, 257/929
• US Class Current: 257/344
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer
• CPC Class Codes: Y10S 257/929 PN junction isolated integrated circuit with isolation walls having minimum dopant concentration at intermediate depth in epitaxial layer, e.g. diffused from both surfaces of epitaxial layer

Abstract

A multiple implant lightly doped drain ("MILDD") field effect transistor is disclosed. The transistor includes a channel, a gate, a dielectric structure that separates the gate from the channel, a source region and a drain region. The drain region has a first drain subregion, a second drain subregion and a third drain subregion. Each drain subregion has a dopant concentration that differs from that of the other two drain subregions. A method of forming the same is also disclosed.

Claims

1. A structure for forming a transistor on a semiconductor substrate comprising:

a channel;

a gate;

a dielectric structure that separates the gate from the channel, said gate having first and second vertical sides perpendicular to the dielectric structure;

a first vertical spacer positioned adjacent to the first vertical side of the gate;

a second vertical spacer positioned adjacent to the first vertical spacer;

a first contact region;

a second contact region having a first subregion, a second subregion and a third subregion, each subregion having a dopant concentration that differs from that of the other two subregions, the channel separating the first contact region from the second contact region, the first subregion being closer to the channel than the second and third subregions, and the second subregion being closer to the channel than the third subregion;

wherein each subregion has a depth and the depth of the first subregion is less than the depth of the second subregion and greater than the depth of the third subregion; and

wherein the first vertical spacer is generally aligned with a boundary of the second subregion, and the second vertical spacer is generally aligned with a boundary of the third subregion.

2. The transistor of claim 1 wherein the first subregion is closer to the channel than the second and third subregions and the second subregion is closer to the channel than the third subregion.

3. The transistor of claim 2 wherein the dopant concentration of the first subregion is less than the dopant concentrations of the second and third subregions.

4. The transistor of claim 3 wherein the dopant concentration of the second subregion is less than the dopant concentration of the third subregion.

5. The transistor of claim 2 wherein each subregion has a depth and the depth of each subregion is substantially similar.

6. The transistor of claim 2 wherein each subregion has a depth and the depth of the first subregion is less than the depths of the second and third subregions.

7. The transistor of claim 6 wherein the depth of the second subregion is less than the depth of the third subregion.

8. The transistor of claim 1 wherein the second contact region further comprises a fourth subregion, the fourth subregion having a dopant concentration that differs from that of the first, second and third subregions.

9. The transistor of claim 1 wherein the transistor is an N-channel device.

10. The transistor of claim 1 wherein the first contact region comprises:

a first subregion,

a second subregion, and

a third subregion, each subregion having a dopant concentration that differs from that of the other two subregions.

11. A transistor, comprising:

a channel;

a gate;

a dielectric structure that separates the gate from the channel;

a first contact region;

a second contact region, the channel separating the first contact region from the second contact region; and

an anti-punchthrough region underlying the second contact region and having a first subregion and a second subregion, each subregion having a dopant concentration that differs from that of the other subregion.

12. A method of forming a transistor on a substrate, comprising the following steps:

forming a dielectric layer overlying the substrate;

forming a gate structure overlying the dielectric layer, the gate structure having a first sidewall and a second sidewall, whereby a first contact region, a channel region and a second contact region are defined within the substrate;

forming an anti-punchthrough region underlying the second contact region and having first and second subregions, each subregion having a dopant concentration that differs from that of the other subregion.

13. A structure for forming a transistor on a semiconductor substrate comprising:

a channel;

a gate;

a dielectric structure that separates the gate from the channel, said gate having first and second vertical sides perpendicular to the dielectric structure;

a first vertical spacer positioned adjacent to the first vertical side of the gate;

a second vertical spacer positioned adjacent to the first vertical spacer;

a first contact region;

a second contact region having a first subregion, a second subregion and a third subregion, each subregion having a dopant concentration that differs from that of the other two subregions, the channel separating the first contact region from the second contact region, wherein the first vertical spacer is generally aligned with a boundary of the second subregion, and the second vertical spacer is generally aligned with a boundary of the third subregion; and

an anti-punchthrough region underlying the second contact region, the anti-punchthrough region having first and second subregions, each subregion of the anti-punchthrough region having a dopant concentration that differs from that of the other subregion of the anti-punchthrough region.