Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging

• US 5,719,438 A
• Filed: 06/06/1995
• Issued: 02/17/1998
• Est. Priority Date: 09/28/1994
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cronin, John Edward, Leas, James Marc, Bertin, Claude Louis, Howell, Wayne John, Beilstein, Kenneth Edward Jr., Perlman, David Jacob
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): OSTROWSKI, DAVID M
• Application Number:
  US08/469,090
• Time in Patent Office: 987 Days
• Field of Search: 257/686, 257/698, 257/723, 257/724, 257/725, 257/777
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Claims

1. An enhanced electronic module comprising:

a semiconductor structure having a substantially planar surface with multiple electrical connect pads thereon; and

a separately formed, thin-film layer bonded to said substantially planar surface of the semiconductor structure such that said separately formed thin-film layer directly electrically connects to said semiconductor structure through said multiple electrical connect pads on said substantially planar surface, and wherein said separately formed thin-film layer comprises a substantially planar film and is parallel to said substantially planar surface of said semiconductor structure.

2. The enhanced electronic module of claim 1, wherein said semiconductor structure comprises a plurality of stacked integrated circuit (IC) chips having a plurality of edge surfaces that at least partially define said substantially planar surface of said semiconductor structure, and wherein said separately formed, thin-film layer electrically attaches to at least some of said plurality of stacked IC chips.

3. The enhanced electronic module of claim 1, further comprising a plurality of electrical contacts disposed on said separately formed thin-film layer for facilitating electrical contact of said enhanced electronic module to circuitry external to said enhanced electronic module.

4. The enhanced electronic module of claim 1, further comprising a plurality of electrical contacts disposed between said substantially planar surface of the semiconductor structure, and said separately formed thin-film layer, wherein at least one electrical contact of said plurality of electrical contacts is electrically insulated from said semiconductor structure for electrically isolating a portion of said semiconductor structure from said thin-film layer.

5. The enhanced electronic module of claim 1, further comprising a temporary support, wherein said separately formed thin-film layer is coupled to said temporary support by a temporary adhesive layer.

6. The enhanced electronic module of claim 1, wherein said separately formed thin-film layer resides on a substrate, said separately formed thin-film layer being disposed between said semiconductor structure and said substrate.

7. The enhanced electronic module of claim 1, wherein said separately formed thin-film layer comprises an active circuit layer, said active circuit layer functioning in association with said semiconductor structure.

8. The enhanced electronic module of claim 1, wherein said separately formed thin-film layer comprises a first metallization layer that electrically connects to said semiconductor structure.

9. The enhanced electronic module of claim 8, wherein said separately formed thin-film layer resides on a substrate, said substrate further including an active circuit layer.

10. The enhanced electronic module of claim 9, wherein said substrate includes a plurality of electrically conductive vias extending between said first metallization layer and said active circuit layer, said plurality of electrically conductive vias electrically connecting said first metallization layer and said active circuit layer.

11. The enhanced electronic module of claim 10, further comprising a plurality of electrical contacts disposed on said active circuit layer for facilitating electrical coupling thereof to a circuit external from said enhanced electronic module.

12. The enhanced electronic module of claim 8, wherein said first metallization layer resides on a passive film.

13. The enhanced electronic module of claim 12, wherein said passive film includes a second metallization layer that electrically connects to said semiconductor structure.

14. The enhanced electronic module of claim 13, wherein said passive film includes a plurality of electrically conductive vias extending between, and electrically connecting, said first metallization layer and said second metallization layer.

15. The enhanced electronic module of claim 13, further comprising a plurality of electrical contacts disposed on said second metallization layer for facilitating electrical coupling thereof to a circuit external from said electronic module.

16. The enhanced electronic module of claim 1, wherein said semiconductor structure includes a second substantially planar surface, and wherein said enhanced electronic module includes a second separately formed thin-film layer bonded to said second substantially planar surface of the semiconductor structure such that the second separately formed thin-film layer electrically attaches to the semiconductor structure.

17. The enhanced electronic module of claim 16, wherein said second separately formed thin-film layer comprises an active circuit layer, said active circuit layer functioning in association with said semiconductor structure.

18. The enhanced electronic module of claim 16, wherein said second separately formed thin-film layer comprises a metallization layer.

19. An electronic package comprising:

an electronic module comprising a plurality of stacked integrated circuit chips having a plurality of edge surfaces that at least partially define a side surface of the electronic module;

an interposer formed separately from said electronic module having a substantially planar main surface and an active circuit layer for providing functions in association with said electronic module; and

wherein said substantially planar main surface of said interposer is electrically and mechanically coupled to said side surface of said electronic module.

20. The electronic package of claim 19, wherein said active circuit layer comprises a processor IC chip for providing a processing function associated with said electronic package.

21. The electronic package of claim 19, wherein said active circuit layer comprises a logic/control IC chip for providing functions associated with said electronic package.

22. The electronic package of claim 19, wherein said side surface of said electronic module has a length x and said substantially planar surface of said interposer has a length y, such that x≦

y.

23. The electronic package of claim 19, wherein said interposer further includes a thin-film metallization layer, said thin-film metallization layer electrically interconnecting at least some of said plurality of stacked integrated circuit chips.

24. The electronic package of claim 19, wherein said interposer further includes internal wiring for electrically interconnecting at least some of said plurality of stacked integrated circuit chips.

25. The electronic package of claim 19, wherein said active circuit layer comprises an IC chip and wherein said interposer electrically connects at least some of said plurality of stacked integrated chips to a predetermined contact surface on said IC chip.

26. The electronic package of claim 19, wherein said interposer further includes electrically conductive vias for electrically connecting said electronic module to said active circuit layer.

27. The electronic package of claim 19, further including means for thermal management attached to said electronic package.

28. The electronic package of claim 19, further including a plurality of electrical contacts disposed on said interposer for facilitating external electrical contact with said electronic package.

29. The electronic package of claim 28, further including one of a plurality of input/output pins and a plurality of leadframe contacts electrically connected to said plurality of electrical contacts for facilitating external electrical contact with said electronic package.

30. The electronic package of claim 28, wherein said side surface of said electronic module lacks means for electrical interconnection between said plurality of IC chips integral therewith.

31. The electronic package of claim 19, further comprising a non-hermetic cap, wherein said non-hermetic cap seals to said interposer.

32. The electronic package of claim 31, wherein said interposer includes a first portion and a second portion, said first portion being non-hermetically sealed by said non-hermetic cap and said second portion being unsealed.

33. The electronic package of claim 19, further comprising a hermetic cap, wherein said hermetic cap hermetically seals to said interposer.

34. The electronic package of claim 33, wherein said interposer includes a first portion and a second portion, said first portion being hermetically sealed by said hermetic cap and said second portion being unsealed.

35. The electronic package of claim 34, wherein the second portion of said interposer further includes electrical contacts disposed thereon for facilitating electrical connection with the electronic package.

36. An electronic package comprising:

an electronic module comprising a plurality of stacked integrated circuit chips, said electronic module having a substantially planar surface;

a cavity substrate having a cavity therein; and

an active integrated circuit chip for providing a function associated with the electronic module, wherein said electronic module and said active integrated circuit chip are recessed within said cavity and said active integrated circuit is mechanically coupled to, and disposed between, said cavity substrate and said substantially planar surface of said electronic module.

37. The electronic package of claim 36, wherein said cavity substrate has a plurality of electrical contacts disposed thereon for facilitating external electrical contact with said electronic package.

38. The electronic package of claim 36, further including means for thermal management attached to said electronic module.

39. The electronic package of claim 36, further including means for hermetically sealing said electronic module within said electronic package for protecting said electronic module from a surrounding environment.

40. The electronic package of claim 36, further including a lid, wherein said lid encloses said cavity and dissipates heat from said electronic module and said active integrated circuit chip.

41. The electronic package of claim 36, further including means for electrical connection between said electronic module and said active integrated circuit chip.

42. The electronic package of claim 36, further including means for electrical connection between said substrate and said active integrated circuit chip.

43. The electronic package of claim 36, further including means for electrical connection between said substrate and said electronic module.

44. The electronic package of claim 36, wherein said plurality of stacked integrated circuit chips of said electronic module have a plurality of edge surfaces, said substantially planar surface of said electronic module being at least partially defined by said plurality of edge surfaces of said plurality of stacked integrated circuit chips.

45. The electronic package of claim 36, wherein said plurality of stacked integrated circuit chips includes an end chip associated therewith, said substantially planar surface of said electronic module being at least partially defined by a planar surface of said end chip of said plurality of stacked integrated circuit chips.

46. The electronic package of claim 36, wherein said cavity substrate has a plurality of wirebond pad levels for efficiently accommodating wirebond connections.

47. The electronic package of claim 36, wherein said cavity substrate has a first wirebond pad level and a second wirebond pad level, the first wirebond pad level accommodating wirebond connections to said electronic module, the second wirebond pad level accommodating wirebond connections to said active integrated circuit chip.

48. The electronic package of claim 36, wherein at least one chip of said plurality of stacked integrated circuit chips is a memory chip for providing a memory function associated with said active integrated circuit chip.

49. The electronic package of claim 36, wherein at least one integrated circuit chip of said plurality of stacked integrated circuit chips is a memory chip, and wherein said active integrated circuit chip is a processor chip, said memory chip providing a cache memory function in association with said processor chip.

50. The electronic package of claim 36, further including a thin-film metallization layer disposed between said electronic module and said active integrated circuit chip for electrically interconnecting at least some of said plurality of stacked integrated circuit chips.

51. The electronic package of claim 36, said package including an interposer disposed between, and mechanically and electrically coupling said electronic module and said active integrated circuit chip.

52. An electronic package comprising:

a cavity substrate having a cavity therein;

a first semiconductor structure; and

a second semiconductor structure,

wherein said first semiconductor structure is supported by said cavity substrate and contained within said cavity of said cavity substrate such that a planar surface of said cavity substrate and a substantially planar surface of said first semiconductor structure are coplanar and together comprise a substantially planar receiving surface to which said second semiconductor structure is mechanically coupled.

53. The electronic package of claim 52, wherein said cavity substrate is sized such that said second semiconductor structure is also recessed within said cavity.

54. The electronic package of claim 52, wherein said first semiconductor structure is an electronic module comprising a plurality of stacked integrated circuit chips, and said second semiconductor structure is an active integrated circuit chip that provides a function associated with the electronic module.

55. The electronic package of claim 52, further including means for electrically connecting said first semiconductor structure and said second semiconductor structure.

56. The electronic package of claim 52, wherein said cavity substrate includes a plurality of electrical contacts disposed thereon, and wherein said electronic package further includes means for electrically connecting said first semiconductor structure and said plurality of electrical contacts.

57. The electronic package of claim 52, wherein said cavity substrate includes a plurality of electrical contacts disposed thereon, and wherein said electronic package further includes means for electrically connecting said second semiconductor structure and said plurality of electrical contacts.

58. The electronic module of claim 52, further including a metallization layer disposed between said substantially planar receiving surface and said second semiconductor structure, wherein said metallization layer electrically connects said first semiconductor structure and said second semiconductor structure.

59. The electronic package of claim 52, wherein said first semiconductor structure is an active integrated circuit chip, and said second structure is an electronic module comprising a plurality of stacked integrated circuit chips.

60. The electronic module of claim 59, further including means for electrical connection disposed between said substantially planar receiving surface and said electronic module, wherein said plurality of stacked integrated circuit chips contains an integrated circuit chip of a first type electrically connected to said substrate, and an integrated circuit chip of a second type electrically connected to said active integrated circuit chip for facilitating an integrated function within said electronic package.

61. The electronic module of claim 60, wherein said active integrated circuit chip is a processor chip, said integrated circuit chip of a first type is a dynamic memory chip, and said integrated circuit chip of a second type is a static memory chip, and wherein said dynamic memory chip provides a general memory function for said processor chip and said static memory chip provides a cache memory function for said processor chip.

62. An electronic package comprising:

an electronic module comprising a plurality of stacked integrated circuit chips, said electronic module having a substantially planar surface;

a cavity substrate having both a cavity and an opening therein; and

wherein said electronic module is recessed within said cavity and supported by said cavity substrate, said substantially planar surface of the electronic module being physically coupled to said cavity substrate.

63. The electronic package of claim 62, further including means for electrically connecting said electronic module and said substrate.

64. The electronic package of claim 62, wherein said opening facilitates an air flow to pass around the electronic module for thermal management thereof.

65. The electronic package of claim 62, further including an active integrated circuit chip electrically coupled and mechanically bonded to said substantially planar surface of the electronic module, wherein said active integrated circuit chip is located within said opening and accessible for maintenance.

66. The electronic package of claim 65, further including a metallization layer disposed between said electronic module and said active integrated circuit chip for electrically interconnecting at least some of said plurality of stacked integrated circuit chips.

67. The electronic package of claim 65, further including means for thermal management at least partially disposed within said opening, wherein said means for thermal management thermally connects to said active integrated circuit chip.

68. The electronic package of claim 67, wherein a seal is disposed between said substrate and said means for thermal management for protecting the electronic module from an external environment.

69. A computer unit comprising:

a processor chip having a substantially planar main surface, said processor chip including a cache memory controller;

a first electronic module comprising a plurality of stacked integrated circuit (IC) chips and having a first substantially planar surface, said first electronic module including a cache memory circuit; and

wherein the substantially planar main surface of the processor chip is mechanically and electrically coupled to the first substantially planar surface of the first electronic module such that the cache memory controller is electrically connected to the cache memory circuit.

70. The computer unit of claim 69, wherein the first electronic module has a second substantially planar surface, said second substantially planar surface having a first plurality of electrical contacts thereon, at least some electrical contacts of said first plurality of electrical contacts being electrically coupled to said processor chip for facilitating electrical contact to said processor chip.

71. The computer unit of claim 70, including an interface chip having a substantially planar main surface mechanically and electrically coupled to the second substantially planar surface of the first electronic module such that said interface chip is electrically coupled to the at least some electrical contacts of the first plurality of electrical contacts electrically coupled to the processor chip.

72. The computer unit of claim 70, including a second processor chip having a substantially planar main surface mechanically and electrically coupled to the second substantially planar surface of the first electronic module such that the second processor chip is electrically coupled to the first electronic module.

73. The computer unit of claim 70, wherein the plurality of stacked IC chips of the first electronic module includes a bussing chip, said bussing chip having a first edge surface parallel with the first substantially planar surface of the first electronic module, and a second edge surface parallel with the second substantially planar surface of the first electronic module, and wherein said bussing chip electrically connects the processor chip coupled to the first substantially planar surface of the first electronic module to the at least some electrical contacts of the first plurality of electrical contacts coupled to the second substantially planar surface of the electronic module.

74. The computer unit of claim 70, wherein the plurality of stacked IC chips of the first electronic module includes an active integrated circuit chip, said active integrated circuit chip having a first edge surface parallel with the first substantially planar surface of the first electronic module, and a second edge surface parallel with the second substantially planar surface of the first electronic module, and wherein said active integrated circuit chip electrically connects the processor chip coupled to the first substantially planar surface of the first electronic module to the at least some electrical contacts of the first plurality of electrical contacts coupled to the second substantially planar surface of the electronic module.

75. The computer unit of claim 70, including an interposer substrate having a substantially planar main surface mechanically coupled to said second substantially planar surface of the first electronic module such that said interposer substrate electrically attaches to the first plurality of electrical contacts and electrically interconnects at least some of the plurality of stacked IC chips of the first electronic module.

76. The computer unit of claim 75, further including an interface cable electrically and mechanically connected to the interposer substrate for facilitating external electrical connection to the computer unit via the interposer substrate.

77. The computer unit of claim 70, further comprising:

a second electronic module comprising a plurality of stacked IC chips and having a first substantially planar surface, said second electronic module including a second memory circuit; and

wherein the first substantially planar surface of the second electronic module is mechanically coupled to the second substantially planar surface of the first electronic module such that the first electronic module and second electronic module are electrically coupled via the first plurality of electrical contacts such that the second electronic module is electrically coupled to the processor chip.

78. The computer unit of claim 77, wherein the second electronic module has a second substantially planar surface, said second substantially planar surface having a second plurality of electrical contacts thereon, at least some of said electrical contacts of said second plurality of electrical contacts electrically coupled through said at least some electrical contacts of the first plurality of electrical contacts of the first electronic module to said processor chip, for providing electrical contact to devices associated with said computer unit.

79. The computer unit of claim 78, including a main memory controller chip having a substantially planar main surface mechanically coupled to the second substantially planar surface of the second electronic module such that said main memory controller chip is electrically coupled to the at least some electrical contacts of the second plurality of electrical contacts of the second electronic module.

80. The computer unit of claim 78, wherein the plurality of stacked IC chips of the second electronic module includes a bussing chip, said bussing chip having a first edge surface parallel with the first substantially planar surface of the second electronic module, and a second edge surface parallel with the second substantially planar surface of the second electronic module, and wherein said bussing chip electrically connects the at least some electrical contacts of the first plurality of electrical contacts of the first electronic module to the at least some electrical contacts of the second plurality of electrical contacts of the second electronic module.

81. The computer unit of claim 69, further comprising a high density interconnect disposed between and mechanically and electrically coupling the first electronic module to the processor chip.

82. The computer unit of claim 69, wherein the first electronic module has a second substantially planar surface, and wherein the computer unit includes an interface cable mechanically and electrically coupled to said second substantially planar surface.

83. The computer unit of claim 69, wherein the cache memory circuit comprises a combined level one ("L1") cache memory circuit and level two ("L2") cache memory circuit.

84. The computer unit of claim 69, wherein the first electronic module includes a main memory circuit, said electrical coupling being such that the main memory circuit functions in association with the processor chip.