Circuit for generating an output signal synchronized to an input signal
First Claim
1. A circuit for generating an output signal synchronized to an incoming periodic signal, said circuit comprising:
- a first node disposed for coupling to said incoming periodic signal;
a second node disposed for coupling to an incoming clock;
a sequence of modules, each said module comprising a latch, an XOR gate, and a time delay, wherein an output of said latch is coupled to said XOR gate;
wherein said first node is coupled to a clock input of each said latch;
wherein said second node is coupled to an input of said latch and an input of said time delay of a first said module, and wherein an output of said time delay of each said module is coupled to an input of said latch of a next said module and an input of said time delay of a next said module; and
a summing node coupled to an output of said XOR gate of each said module.
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Accused Products
Abstract
A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.
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Citations
27 Claims
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1. A circuit for generating an output signal synchronized to an incoming periodic signal, said circuit comprising:
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a first node disposed for coupling to said incoming periodic signal; a second node disposed for coupling to an incoming clock; a sequence of modules, each said module comprising a latch, an XOR gate, and a time delay, wherein an output of said latch is coupled to said XOR gate; wherein said first node is coupled to a clock input of each said latch; wherein said second node is coupled to an input of said latch and an input of said time delay of a first said module, and wherein an output of said time delay of each said module is coupled to an input of said latch of a next said module and an input of said time delay of a next said module; and a summing node coupled to an output of said XOR gate of each said module. - View Dependent Claims (2, 3)
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4. A circuit, comprising:
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means for receiving an incoming signal; means for sampling a set of parallel clock signals; means for combining an output of said means for sampling with said parallel clock signals; means for summing an output of said means for combining; and means for shaping an output of said means for summing wherein said means for shaping comprises a comparator and a reference signal. - View Dependent Claims (5, 6, 7, 8, 9)
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10. A circuit for generating an output signal synchronized to an incoming signal, said circuit comprising:
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means for sampling a plurality of clock signals at a transition of said incoming signal, to provide corresponding sample bits; first means for combining said clock signals with said corresponding sample bits, to provide altered clock signals; and second means for combining said altered clock signals into an output signal comprising means for comparing a sum of said altered clock signals with a reference signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A circuit for generating an output signal synchronized to an incoming signal, said circuit comprising:
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a node disposed for coupling to said incoming signal; a plurality of latches, each said latch coupled to one of a plurality of clock signals and having a triggering input coupled to said node; a plurality of logic gates, each said logic gate coupled to one of said clock signals and to one of said latches, and each said logic gate having an logic output; an output node coupled to all of said logic outputs; and a summing node coupled to all of said logic outputs; and a comparator coupled to said summing node, to a reference signal, and to said output node.
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18. A circuit for generating an output signal synchronized to an incoming signal, said circuit comprising:
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a plurality of modules each having a latch triggered by said incoming signal, a time delay, and an XOR gate; wherein said time delay of each said module is coupled to said time delay of a previous said module and to said latch of a next said module; wherein said XOR gate of each said module is coupled to said latch of said module and to said time delay of said previous module; and a summing node coupled to each said latch. - View Dependent Claims (19, 20)
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21. A method for generating an output signal synchronized to an incoming signal, said method comprising:
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sampling a plurality of clock signals at a transition of said incoming signal, to provide corresponding sample bits; combining said clock signals with said corresponding sample bits, to provide altered clock signals; and combining said altered clock signals into an output signal wherein said second step of combining comprises comparing a sum of said altered clock signals with a reference signal. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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Specification