Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory

• US 5,719,531 A
• Filed: 10/30/1996
• Issued: 02/17/1998
• Est. Priority Date: 06/17/1993
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Iwanari, Shunichi, Kikukawa, Hirohito, Yamada, Toshio, Kotani, Hisakazu, Akamatsu, Hironori, Sawada, Akihiro, Agata, Masashi
• Primary Examiner(s): Mottola, Steven
• Application Number:
  US08/739,841
• Time in Patent Office: 475 Days
• Field of Search: 330/69, 330/252, 330/253, 330/261, 330/297, 323/271, 323/282
• US Class Current: 330/297
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements

Abstract

In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Claims

1. An amplifying circuit for amplifying a pair of differential signals inside a semiconductor integrated circuit, comprising:

a pair of differential input terminals for accepting said pair of differential signals;

an amplifier for amplifying the pair of differential signals inputted via said pair of differential input terminals;

a pair of differential output terminals for outputting the pair of differential signals which have been amplified by said amplifier; and

a power source controller for controlling current supply to said amplifier based on outputs from said pair of differential output terminals.

2. An amplifying circuit according to claim 1, wherein said power source controller comprises first and second PMOS transistors which are connected in series to each other and which are interposed between a power source line and said amplifier, wherein

said first PMOS transistor has its gate connected to one of said pair of differential output terminals, and

said second PMOS transistor has its gate connected to the other of said pair of differential output terminals.