System and method for the verification of a digital control system

• US 5,719,559 A
• Filed: 06/23/1995
• Issued: 02/17/1998
• Est. Priority Date: 06/23/1995
• Status: Expired due to Term

• Current Assignee: Flowserve Management Company (Flowserve Corporation)
• Original Assignee: Limitorque Corp. (Schneider Electric SE)
• Inventors: Dolenti, William T., Adams, David V. IV, Talbott, Kenneth R., Gahagen, Thomas D.
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): WILSON JR, WILLIAM HALL
• Application Number:
  US08/494,156
• Time in Patent Office: 970 Days
• Field of Search: 340/825.06, 340/825.16, 364/509, 364/510, 364/132, 73/861.08, 137/487.5, 251/129.04, 251/129.05, 251/129.01, 395/185.02, 395/185.01, 395/184.01, 318/565
• US Class Current: 340/3.43
• CPC Class Codes: G05B 19/048 Monitoring; Safety
• CPC Class Codes: G05B 2219/24078 Debounce, correct periodicity of command
• CPC Class Codes: G05B 2219/24079 Detect correct command wave form
• CPC Class Codes: G05B 2219/24081 Detect valid sequence of commands
• CPC Class Codes: G05B 2219/24082 Detect if driver, actuation circuit is correct
• CPC Class Codes: G05B 2219/24083 Detect if actuators are correct, react
• CPC Class Codes: G05B 2219/24128 Command and intermediate error feedback used to verify correct execution
• CPC Class Codes: G05B 2219/25242 Relay

Abstract

A verification system monitors the operation of a digital control system in order to insure proper operation. The verification system receives control signals and monitors these control signals to determine whether operation is proper. The digital control system is adapted for operational control of various equipment. The verification system monitors control signals received from the digital control system as well as the status of the equipment, where appropriate, in determining whether the operation of the digital control system is proper. The verification system includes various portions which monitor the control signals at various stages. If there is an error detected at one of the stages, an error signal is generated which prevents operation of the associated equipment.

Claims

1. A verification system for use in a digital control system, the digital control system providing at least one control signal to said verification system, said verification system comprising:

control signal validation means for verifying said control signal received from said digital control system;

drive means for providing at least one operating signal in response to at least one drive signal;

drive validation means for verifying a condition of said drive means;

actuating means responsive to said operating signal for providing at least one output signal from said verification system;

sensor means responsive to said output signal for identifying a condition corresponding to said output signal;

error detection means responsive to said control signal validation means, drive validation means and sensor means for providing at least one error signal; and

drive signal generating means responsive to said control signal validation means and said error detection means for providing said at least one drive signal to said drive means.

2. A verification system according to claim 1, wherein said control signal defines a waveform of a defined configuration including at least one high period and at least one low period.

3. A verification system according to claim 2, wherein said control signal validation means comprises period monitoring means for monitoring said high periods and said low periods of said control signal against defined limits, wherein said period monitoring means provides at least one error signal to said error detection means when said defined limits are exceeded.

4. A verification system according to claim 3, wherein said control signal validation means further comprises validation and sequence monitoring means for monitoring said configuration of said waveform for identifying waveform validity against defined valid waveforms, and for identifying a sequence of valid waveforms against defined allowable sequences, wherein said validation and sequence monitoring means generates at least one verified control signal to said drive signal generating means when the configuration of said waveform corresponds to said defined valid waveforms and defined allowable sequences, and generates at least one error signal to said error detection means when the configuration of said waveform deviates from either said defined valid waveforms or defined allowable sequences.

5. A verification system according to claim 3, wherein said period monitoring means comprises means for debouncing said control signal.

6. A verification system according to claim 1 wherein said sensing means includes a first detection means for identifying a condition of operation of said actuating means and a second detection means for identifying a condition of operation of said digital control system, wherein said error detection means is responsive to said first detection means of said sensing means.

7. A verification system according to claim 6, wherein said actuating means comprises a plurality of relays for generating a plurality of output signals, with at least a first relay providing at least one output to said first detection means and at least a second relay providing at least one output to said second detection means.

8. A verification system according to claim 7, wherein said actuating means comprises four relays, with three relays being in communication with said first detection means and one relay being in communication with said second detection means.

9. A digital control system for electro-mechanical equipment comprising:

control means for generating at least one control signal;

control signal validation means receiving said control signal for verifying said control signal and generating at least one verified control signal in response thereto;

drive means responsive to at least one drive signal for providing at least one operating signal;

drive validation means responsive to said operating signal for verifying a condition of operation of said drive means and generating at least one verified drive signal in response thereto;

actuating means responsive to said operating signal for generating at least one output signal for controlling said electro-mechanical equipment;

sensor means including a first detection means responsive to said output signal for verifying a condition of operation of said actuating means and generating at least one verified output signal in response thereto, said sensor means further including a second detection means responsive to said output signal for identifying a condition of operation of said electro-mechanical equipment associated with said digital control system;

error detection means responsive to said verified control signal of said control signal validation means, verified drive signal of said drive validation means and said verified output signal of said sensor means for generating at least one error signal; and

drive signal generating means responsive to said verified control signal of said control signal validation means and said error signal from said error detection means for generating said at least one drive signal to said drive means.

14. A digital control system according to claim 9, wherein said actuating means comprises at least one relay.

15. A digital control system according to 14, wherein said actuating means comprises a plurality of relays for generating a plurality of output signals, with at least a first relay providing at least one output signal to said first detection means and at least a second relay providing at least one output signal to said second detection means.

16. A digital control system according to claim 15, wherein said output signal of said first relay provides a condition of operation of said electro-mechanical equipment.

17. A digital control system according to claim 9, wherein said control means receives said error signal from said error detection means, with said control means further including means for identifying a condition of said error detection means.

10. A digital control system according to claim wherein said control signal defines a waveform of a defined configuration including at least one high period and at least one low period.

11. A digital control system according to claim 10, wherein said control signal validation means comprises period monitoring means for monitoring said high periods and said low periods of said control signal against defined limits, wherein said period monitoring means provides at least one error signal to said error detection means when said defined limits are exceeded.

12. A digital control system according to claim 11, wherein said control signal validation means further comprises validation and sequence monitoring means for monitoring said configuration of said waveform for identifying waveform validity against defined valid waveforms, and for identifying a sequence of valid waveforms against defined allowable sequences, wherein said validation and sequence monitoring means generates said verified control signal to said drive signal generating means when the configuration of said waveform corresponds to said defined valid waveforms and defined allowable sequences, and generates at least one error signal to said error detection means when the configuration of said waveform deviates from either said defined valid waveforms or defined allowable sequences.

13. A digital control system according to claim 11, wherein said period monitoring means comprises means for debouncing said control signal.

18. A method for verifying operation of a digital control system for electro-mechanical equipment, said method including the steps of:

generating at least one control signal;

verifying said control signal and generating at least one verified control signal in response thereto;

generating at least one operating signal in response to at least one drive signal;

verifying said operating signal and generating at least one verified drive signal in response thereto;

generating at least one output signal in response to said operating signal for controlling said electro-mechanical equipment;

verifying said output signal and generating at least one verified output signal in response thereto;

generating at least one error signal in response to said verified control signal, verified drive signal and verified output signal; and

generating said at least one drive signal in response to said verified control signal and said error signal.

19. A method according to claim 18, wherein the step of verifying said output signal further includes the step of identifying a condition of operation of said electro-mechanical equipment associated with said digital control system.

20. A method according to claim 18, wherein said control signal defines a waveform of a defined configuration including at least one high period and at least one low period, wherein the method further includes the steps of monitoring said high periods and said low periods of said control signal against defined limits and generating at least one error signal when said defined limits are exceeded.

21. A method according to claim 20 further including the step of monitoring the configuration of said waveform for identifying waveform validity against defined valid waveforms and for identifying a sequence of valid waveforms against defined allowable sequences, the method further including the step of generating said verified control signal when the configuration of said waveform corresponds to said defined valid waveforms and defined allowable sequences, and generating at least one error signal when the configuration of said waveform deviates from either said defined valid waveforms or defined allowable sequences.

22. A method according to claim 20, wherein the step of monitoring said waveform further includes the step of debouncing said control signal.

23. A method according to claim 18, wherein the step of verifying said output signal and generating a verified output signal further includes the step of identifying a condition of said verified output signal.

24. A method according to claim 18, wherein the step of generating an error signal further includes the step of identifying a condition of operation corresponding to said error signal.