Semiconductor package with a bridge for chip area connection

• US 5,719,748 A
• Filed: 06/28/1995
• Issued: 02/17/1998
• Est. Priority Date: 06/28/1995
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Spielberger, Richard K., Dunaway, Thomas J., Cullinan, Deborah A.
• Primary Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US08/495,138
• Time in Patent Office: 965 Days
• Field of Search: 174/68.2, 174/250, 174/253, 174/254, 174/255, 174/256, 174/258, 174/260, 174/261, 174/268, 257/700, 257/690, 257/691, 257/692, 257/723, 257/724, 257/786, 257/758, 257/684, 361/761, 361/763, 361/764, 361/767, 361/768-770, 361/771, 361/772, 361/774, 361/775, 361/776, 361/777, 361/778, 361/780, 361/783, 361/790, 361/784, 361/749, 361/748, 361/792-795, 361/803, 361/782, 439/47, 439/48, 439/67, 439/69, 439/74, 439/77
• US Class Current: 361/764
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A semiconductor package including a base having a chip receiving portion and a surrounding portion; a bridge having conductive strips extending over the chip and supported at the surrounding portion; wires connect the conductive strips to power and ground; and wires connect the conductive strips to chip area power and ground bonding pads. Decoupling capacitors may be mounted on the base.

Claims

1. In a semiconductor package of the type having a base having a recessed central portion for receiving a chip and a perimeter portion having electrical connection means which are connected through said base to outer connection means, the improvement comprising:

a bridge extending over said semiconductor chip and supported at said perimeter portion, said bridge having a plurality of conductive strips thereon, said strips facing away from said chip;

a first one of said plurality of conductive strips connected to a first reference voltage at said base;

said chip having a plurality of bonding pads which enable external connection of circuits contained in said chip, said bonding pads located adjacent said bridge; and

means for selectively connecting said plurality of conductive strips to said bonding pads.

2. Semiconductor package of claim 1 wherein said semiconductor chip has a length dimension and a width dimension and said bridge is formed with a first member parallel to said length dimension and a second member parallel to said width dimension with said first member and said second member in a cross arrangement.

3. Semiconductor package of claim 2 wherein said means for selectively connecting is wire bond.

4. Semiconductor package of claim 3 wherein said bridge comprises a ceramic material and said perimeter portion is shaped for complimentary receipt of said bridge.

5. Semiconductor package of claim 3 wherein said means for connecting a first one of said plurality of conductive strips to a first reference voltage and said means for connecting a second one of said plurality of conductive strips to a second reference voltage comprises wire bond means.

6. Semiconductor package of claim 5 wherein said means for selectively connecting is wire bond.

7. Semiconductor package of claim 5, further comprising means for mounting at least one decoupling capacitor at said surrounding portion.

8. A semiconductor package for making electrical connections to a semiconductor die, comprising:

a base having a perimeter portion and a central portion, said central portion recessed for receiving a semiconductor die;

said die having a first edge and a second edge perpendicular to said first edge;

a bridge extending over said semiconductor die, said bridge formed of insulative material and having a first member and a second member, with said first member and said second member forming a cross having ends, with said ends supported at said perimeter;

first and second conductive strips formed on said bridge, said first conductive strip connected to a first reference voltage and said second conductive strip connected to a second reference voltage;

said die having a plurality of bonding pads which enable external connection of circuits contained in said chip, said bonding pads located adjacent said bridge; and

means for selectively connecting said plurality of conductive strips to said bonding pads.

9. Semiconductor package of claim 8 wherein said bridge comprises a ceramic material and said perimeter portion is shaped for complimentary receipt of said bridge.

10. Semiconductor package of claim 8, further comprising means for mounting at least one decoupling capacitor at said surrounding portion.