Performance throttling to reduce IC power consumption

• US 5,719,800 A
• Filed: 06/30/1995
• Issued: 02/17/1998
• Est. Priority Date: 06/30/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Valentine, Robert, Mittal, Millind
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US08/497,853
• Time in Patent Office: 963 Days
• Field of Search: 364/707, 395/750
• US Class Current: 713/321
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

The power consumed within an integrated circuit (IC) is reduced without substantial impact on its performance for typical applications by throttling the performance of particular functional units within the IC. Artificial worst-case power consumption is reduced by throttling down the activity levels of long-duration sequences of high-power operations. The recent utilization levels of particular functional units within an IC are monitored--for example, by computing each functional unit'"'"'s average duty cycle over its recent operating history. If this activity level is greater than a threshold, then the functional unit is operated in a reduced-power mode. The threshold value is set large enough to allow short bursts of high utilization to occur without impacting performance. The invention allows an integrated circuit to dynamically make the tradeoff between high-speed operation and low-power operation, by throttling back performance of localized functional units when their utilization exceeds a sustainable level. Additionally, this dynamic power/speed tradeoff can be optimized across multiple functional units within an IC or among multiple ICs within a system. Additionally, this dynamic power/speed tradeoff can be altered by providing software control over throttling parameters.

Claims

1. A microprocessor with controlled power consumption, comprising:

a storage unit configured to store a dynamically alterable activity threshold;

a floating-point unit operable to compute floating point arithmetic in a normal mode and in a reduced-power mode;

an activity monitor, coupled to said storage unit, operable to monitor utilization of said floating-point unit; and

a mode controller, coupled to said storage unit and to said activity monitor, operable to place said storage unit in said reduced-power mode when said utilization is greater than said activity threshold.

2. The microprocessor of claim 1, further comprising:

a unit, coupled to said floating-point unit and responsive to a power-reduction signal from said mode controller, to reduce the rate at which said floating-point unit is clocked when said floating-point unit is in said reduced-power mode.

3. A microprocessor with controlled power consumption, comprising:

an activity threshold memory configured to store a dynamically alterable threshold;

a cache memory operable to store information also stored in an external memory and operable in a normal mode and in a reduced-power mode;

an activity monitor, coupled to said cache memory, operable to produce an activity level indicative of utilization of said cache memory; and

a mode controller, coupled to said activity threshold memory and to said activity monitor, operable to place said cache memory in said reduced-power mode when said activity level is greater than said activity threshold.

4. The microprocessor of claim 3, further comprising:

a unit, coupled to said cache memory and responsive to a power-reduction signal from said mode controller, operable to access said external memory when said cache memory is in said reduced-power mode.

5. The microprocessor of claim 3, further comprising:

a unit, coupled to said cache memory and responsive to a power-reduction signal from said mode controller, operable to throttle prefetches of said information into said cache memory when said cache memory is in said reduced-power mode.

6. The microprocessor of claim 3 wherein said stored information comprises instructions, and said microprocessor further comprises:

an instruction-execution unit, coupled to said cache memory, operable to execute said instructions.

7. The microprocessor of claim 3 wherein said stored information comprises data, and said microprocessor further comprises:

a data-computation unit, coupled to said cache memory, operable to perform computations on said data.

8. A microprocessor with controlled power consumption, comprising:

a data-computation unit, operable to perform computations on data stored in an external memory;

a data cache, coupled to said data-computation unit and to said external memory, operable to store said data;

an activity monitor, coupled to said data cache, operable to indicate the recent utilization of said data cache;

an instruction-execution unit, operable to execute instructions from said external memory;

an instruction cache, coupled to said instruction-execution unit and to said external memory, operable to store said instructions and operable in a normal mode and in a reduced-power mode; and

a mode controller, coupled to said instruction cache and to said activity monitor, operable to place said instruction cache in said reduced-power mode when said recent utilization is greater than a threshold.

9. A microprocessor with controlled power consumption, comprising:

an instruction-execution unit, operable to speculatively execute instructions;

an activity monitor, coupled to said instruction-execution unit, operable to indicate the recent utilization of said instruction-execution unit; and

a mode controller, coupled to said instruction-execution unit and to said activity monitor, operable to throttle said speculative instruction execution, and not to throttle non-speculative instruction execution, when said recent utilization is greater than a threshold.

10. An IC having controlled power consumption, comprising:

a functional unit operable in a normal mode and in a reduced-power mode;

an activity monitor, coupled to said functional unit, operable to indicate utilization of said functional unit; and

a mode controller, coupled to said functional unit and to said activity monitor, operable to place said functional unit in said reduced-power mode when said utilization is greater than a threshold indicated by a throttling parameter associated with said functional unit, said throttling parameter being dynamically adjustable to alter said threshold.

11. The IC of claim 10, further comprising:

a unit, coupled to said functional unit and responsive to said mode controller, operable to reduce the rate at which said functional unit is clocked when said functional unit is in said reduced-power mode.

12. The IC of claim 10 wherein said functional unit comprises a cache memory to store information also stored in an external memory, and said IC further comprises:

a unit, coupled to said functional unit and responsive to said mode controller, operable to access external memory when said functional unit is in said reduced-power mode.

13. The IC of claim 10 wherein said functional unit comprises a cache memory to store information from an external memory, and said IC further comprises:

a unit, coupled to said functional unit and responsive to said mode controller, operable to throttle prefetches from said external memory to said cache memory when said functional unit is in said reduced-power mode.

14. The IC of claim 10, wherein said functional unit is operable to perform speculative operations, and said IC further comprises:

a unit, coupled to said functional unit and responsive to said mode controller, operable to throttle said speculative operations when said functional unit is in said reduced-power mode.

15. The IC of claim 10, wherein

said functional unit is operable in cycles;

and

said activity monitor indicates said utilization by changing an activity level by a first amount for each of said cycles that said functional unit is active and changing said activity level by a second amount for each of said cycles that said functional unit is inactive, said throttling parameter comprising said activity level.

16. The IC of claim 15, further comprising:

a power coordinator operable dynamically to alter said throttling parameter.

17. An integrated circuit with controlled power consumption, comprising:

a functional means for performing a function operable in a normal mode and in a reduced-power mode;

a monitor means, coupled to said functional means, for calculating an activity level indicative of utilization of said functional means; and

a control means, coupled to said functional means and to said monitoring means, operable to place said functional means in said reduced-power mode when said activity level is greater than a predetermined threshold, the predetermined threshold being dynamically adjustable.

18. A method of controlling power consumption within an integrated circuit (IC), comprising:

monitoring utilization of a functional unit within said IC;

dynamically adjusting an activity threshold associated with the functional unit;

comparing said utilization with said activity threshold;

placing said functional unit in a normal mode when said utilization is less than said activity threshold; and

placing said functional unit in a reduced-power mode when said utilization is greater than said activity threshold.

19. The method of claim 18, wherein said reduced-power mode comprises reducing the rate at which said functional unit is clocked.

20. The method of claim 18, wherein said functional unit comprises a cache memory and said step of placing said cache memory in said reduced-power mode comprises diverting accesses to the cache memory to an external memory.

21. The method of claim 18, wherein said functional unit performs speculative operations and said step of placing said functional unit in said reduced-power mode comprises throttling execution of said speculative operations.

22. The method of claim 18, wherein said monitoring comprises changing an activity level by a first amount for each cycle in which said functional unit is active and changing said activity level by a second amount for each cycle in which said functional unit is inactive.

23. The method of claim 22, further comprising:

dynamically determining said first amount.

24. The method of claim 22, further comprising:

dynamically determining said second amount.

25. An integrated circuit (IC) having controlled power consumption, comprising:

a first functional unit within said IC;

a second functional unit within said IC, said second functional unit being operable in a normal mode and in a reduced-power mode and having an activity level related to an activity level of the first functional unit;

an activity monitor within said IC, coupled to said first functional unit, operable to produce an activity level indicative of the activity level of said first functional unit; and

a controller within said IC, coupled to said second functional unit and to said activity monitor, operable to place said second functional unit in said reduced-power mode when said activity level of said first functional unit is greater than a threshold.

26. An integrated circuit (IC) having controlled power consumption, comprising:

a plurality of functional units each operable in a normal mode and in a reduced-power mode;

a plurality of local power controllers, each associated with at least one of said functional units and each having throttling parameters, operable to control the power consumption of said associated functional unit in accordance with the current values of said throttling parameters; and

a power coordinator, coupled to at least two of said local power controllers, operable to read a throttling parameter in a first one of said coupled local power controllers and, based thereon, operable to alter a throttling parameter in a second one of said coupled local power controllers.

27. A method of controlling the power consumption of an integrated circuit (IC), comprising:

monitoring utilization of a first functional unit within said IC to produce a first activity level; and

controlling the mode of operation of a second functional unit within said IC, said second functional unit having a second activity level related to said first activity level of said first functional unit, and being operable in a normal mode and in a reduced-power mode by placing said second functional unit in said reduced-power mode when said first activity level is greater than a threshold.

28. A method of controlling power consumption of an integrated circuit (IC), comprising:

controlling the mode of operation of a plurality of functional units within said IC based on a set of throttling parameters, each said functional units being operable in a normal mode and in a reduced-power mode; and

coordinating the power consumption of said plurality of functional units by dynamically monitoring and altering said throttling parameters.

29. An integrated circuit (IC) with power consumption controllable by a processor, comprising:

a functional unit operable in a normal mode and in a reduced-power mode;

an activity monitor, coupled to said functional unit, having a throttling parameter, operable to generate an activity level indicative of utilization of said functional unit;

a memory unit configured to store a throttling parameter, said throttling parameter being dynamically alterable by said processor, and

a mode controller, coupled to said functional unit and to said activity monitor, operable to control said mode of said functional unit responsive to said activity level and to said throttling parameter.

30. The IC of claim 29, wherein

said command occurs responsive to platform software executing on said processor.

31. The IC of claim 29, wherein

said command occurs responsive to operating system software executing on said processor.

32. The IC of claim 29, wherein

said command occurs responsive to applications software executing on said processor.