Flash EEPROM system

• US 5,719,808 A
• Filed: 03/21/1995
• Issued: 02/17/1998
• Est. Priority Date: 04/13/1989
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/407,916
• Time in Patent Office: 1,064 Days
• Field of Search: 365/185, 365/218, 365/900, 365/230.03, 365/104, 365/185.22, 365/185.29, 365/185.33
• US Class Current: 365/185.33
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of operating a memory system having an array of EEPROM cells divided into multiple non-overlapping sectors that individually contain a plurality of said cells sufficient to store multiple bytes of data and which are erasable together, comprising:

(a) initially tagging a plurality of said multiple sectors to be erased,

(b) subjecting the EEPROM cells of the tagged sectors in parallel to erase voltages while the remaining multiple sectors are not so subjected,

(c) thereafter verifying whether individual ones of the tagged sectors have become erased,

(d) clearing the tags from those sectors which are verified to have become erased while continuing to subject remaining tagged sectors to erase voltages, and

(e) repeating operations (b) through (d) until the tags have been cleared from all of the initially tagged sectors, thereby to erase all the initially tagged sectors.

2. The method of claim 1, which additionally comprises maintaining an identification of those of said multiple sectors that are defective, and avoiding subjecting such identified sectors to the erase voltages.

3. The method of claim 1, which additionally comprises limiting the number of sectors that are erased in parallel in response to a predetermined power capability of the memory system.

4. The method of any one of claims 1-3 wherein operation (a) includes initially tagging a plurality of but less than all of said multiple sectors to be erased.

5. A flash EEPROM system, comprising:

a memory controller and system address bus,

multiple sectors of flash EEPROM cells that are individually addressable through said address bus to be erased and which individually store multiple bytes of data, the cells of the individual sectors being erasable together when the individual sectors are addressed,

a logic circuit configured to address and enable for erasure, in response to signals from the controller, any combination of a plurality of but less than all of said multiple sectors, and

an erase circuit coupled to erase together all the enabled sectors without erasing others of the multiple sectors that are not so enabled.

6. The system of claim 5, wherein the logic circuit includes a register associated with individual ones of the sectors to tag its respective sector as enabled for erasure.

7. The system of claim 6, which additionally comprises a verifying circuit that indicates when individual sectors have been erased, and wherein the logic circuit is responsive to said verifying circuit for clearing tags from those registers of a particular combination of sectors which are verified to be erased while maintaining the tags in the registers associated with others of said particular combination of sectors.

8. The system of claim 5, which additionally comprises a verifying circuit that indicates when individual sectors have been erased, and wherein the logic circuit is responsive to said verifying circuit for disabling from further erase those of a particular combination of sectors which are verified to be erased while maintaining enabled for erase others of said particular combination of sectors.

9. The system of any one of claims 5-8, wherein the erase circuit is coupled to erase all the enabled sectors in parallel.

10. The system of any one of claims 5-8, wherein the multiple sectors of EEPROM cells include substantially all the EEPROM cells in the system.

11. A flash EEPROM system, comprising:

multiple sectors of flash EEPROM cells that are individually addressable for erasure and which individually store multiple bytes of data, the cells of the individual sectors being erasable together,

a logic circuit configured to enable erasure of any one of multiple different combinations of a plurality of but less than all of said multiple sectors, and

an erase circuit coupled to erase together all the enabled sectors of said any one combination without erasing others not in said any one combination.

12. The system of claim 11, wherein said logic circuit includes a plurality of registers that individually contain a tag indicating whether an associated sector is enabled for erasure or not.

13. The system of claim 12, which additionally comprises a verifying circuit that indicates when individual sectors have been erased, and wherein the logic circuit is responsive to said verifying circuit for clearing tags from those registers of a particular combination of sectors which are verified to be erased while maintaining the tags in the registers associated with others of said particular combination of sectors.

14. The system of claim 11, which additionally comprises a verifying circuit that indicates when individual sectors have been erased, and wherein the logic circuit is responsive to said verifying circuit for disabling from further erase those of a particular combination of sectors which are verified to be erased while maintaining enabled for erase others of said particular combination of sectors.

15. The system of any one of claims 11-14, wherein the erase circuit is coupled to erase all the enabled sectors in parallel.

16. A method of operating a memory system having an array of EEPROM cells divided into multiple non-overlapping sectors that individually contain a plurality of said cells sufficient to store multiple bytes of data and which are erasable together, comprising:

(a) designating a combinations of a plurality of but less than all of said multiple sectors to be erased,

(b) erasing the combination of sectors without erasing others of said multiple sectors,

(c) after the combination of sectors has been erased, writing data in at least some of the erased combination of sectors, and

(d) repeating the operations of (a) through (c) with another combinations of sectors.

17. The method of claim 16, wherein the operation of erasing the combination of sectors includes:

verifying when individual sectors in the combination of sectors become erased,

terminating further erasing of such verified sectors while continuing to erase others of the combination of sectors, and

terminating further erasing of any of the combination of sectors when all of the combination of sectors have been verified as erased.

18. The method of claim 17, wherein designating the combination of sectors includes setting a tag bit for individual ones of the sectors to be erased, and wherein terminating further erasing of the verified sectors includes clearing the tag bits for the sectors which have been verified.

19. (New) The method of claim 16, wherein designating the combination of sectors includes setting a tag bit for individual ones of the sectors to be erased, and wherein erasing the combination of sectors includes clearing the tag bits associated with the sectors that have been erased.

20. The method of claim 16, which additionally comprises maintaining an identification of those of said multiple sectors that are defective, and wherein erasing the combination of sectors includes avoiding the identified defective sectors.

21. The method of any one of claims 16-20, wherein erasing the combination of sectors includes erasing the combination of sectors in parallel.

22. The method of claim 21, wherein designating the combination of sectors includes limiting the number of sectors that are erased in parallel in response to a predetermined power capability of the memory system.

23. A method of operating a memory system having an array of EEPROM cells divided into multiple non-overlapping sectors that individually contain a plurality of said cells sufficient to store multiple bytes of data and which are erasable together, comprising:

(a) designating a combinations of any one of multiple different combinations of a plurality of but less than all of said multiple sectors to be erased,

(b) erasing the combination of sectors without erasing others of said multiple sectors, and

(c) after the combination of sectors has been erased, writing data in at least some of the erased combination of sectors.