Semiconductor memory device capable of storing high potential level of data

• US 5,719,814 A
• Filed: 09/25/1996
• Issued: 02/17/1998
• Est. Priority Date: 10/31/1995
• Status: Expired due to Term

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: NEC Corporation
• Inventors: Ishikawa, Toru
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/719,880
• Time in Patent Office: 510 Days
• Field of Search: 365/149, 365/190, 365/205, 365/230.06, 327/51, 327/57
• US Class Current: 365/205
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a semiconductor memory device, a row decoder is connected to a plurality of word lines to select one of the plurality of word lines in response to a row address. A word line driving section drives, in response to a row address strobe signal, the selected word line to a first potential higher by a predetermined potential than a predetermined second potential, for a read or write operation to a selected memory cell connected to the selected word line and a selected pair of bit lines. The second potential is higher than a power supply higher side potential. A sense amplifier activating section issues sense amplifier activating signals for the write operation to the selected memory cell in response to a sense control signal such that a data having a potential higher than the power supply higher side potential can be written or rewritten in the selected memory cell. Each of a plurality of sense amplifiers amplifies the data on corresponding pair of bit lines in response to the sense amplifier activating signals. In the read operation, the read data is outputted from an input/output section via a column selecting section for selecting and connecting one of the plurality of pairs of bit lines to the input/output section in response to a column address.

Claims

1. A semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells arranged in a matrix;

a plurality of pairs of bit lines, the memory cells in each of columns of said matrix being associated with one of said plurality of pairs of bit lines corresponding to the column;

a plurality of word lines, the memory cells in each of rows of said matrix being connected to one of said plurality of word lines corresponding to the row;

sense amplifier means comprised of a plurality of sense amplifiers respectively provided for said plurality of pairs of bit lines, wherein each of said plurality of sense amplifiers amplifies a data on its corresponding pair of bit lines in response to sense amplifier activating signals;

a row decoder connected to said plurality of word lines, for selecting one of said plurality of word lines in response to a row address;

input/output means provided to be connectable to said plurality of pairs of bit lines, for inputting or outputting a data;

column selecting means for selecting and connecting one of said plurality of pairs of bit lines to said input/output means in response to a column address;

word line driving means for driving, in response to a row address strobe signal, a word line selected by said row decoder to a first potential which is higher by a predetermined potential than a second predetermined potential, for a read or write operation to one memory cell connected to said selected word line and said pair of bit lines selected by said column selecting means as a selected memory cell, said second potential being higher than a power supply higher side potential; and

sense amplifier activating means for issuing said sense amplifier activating signals to said sense amplifier means for the write operation to said selected memory cell in response to a sense control signal such that one of the bit lines of said selected pair is driven to said second potential.

2. A semiconductor memory device according to claim 1, wherein said word line driving means drives said selected word line to said first potential while said word line is in a selected state.

3. A semiconductor memory device according to claim 2, wherein said sense amplifier activating means issues said sense amplifier activating signals to said sense amplifier means in response to said sense control signal such that one of said selected pair of bit lines is driven to said second potential when a data read from said selected memory cell is rewritten in said selected memory cell or a data is written in said selected memory cell.

4. A semiconductor memory device according to claim 1, wherein said word line driving means drives said selected word line to said first potential during a first predetermined time period when a data is read from said selected memory cell and a second predetermined time period when the read data is re-written in said selected memory cell or a data is written in said selected memory cell.

5. A semiconductor memory device according to claim 4, wherein said sense amplifier activating means issues said sense amplifier activating signals to said sense amplifier means in response to said sense control signal such that one of said selected pair of bit lines is driven to said second potential during a third predetermined time period corresponding to said second predetermined time period.

6. A semiconductor memory device according to claim 4, wherein said word line driving means drives said selected word line to a third potential which is lower than said power supply higher side potential during a time period between said first predetermined time period and said second predetermined time period.

7. A semiconductor memory device according to claim 1, further comprising an internal voltage dropping circuit for dropping a supply voltage externally supplied, said second potential corresponding to said supply voltage externally supplied.

8. A semiconductor memory device according to claim 1, further comprising an internal voltage boosting circuit for boosting a supply voltage externally supplied, said second potential corresponding to the boosted supply voltage.

9. A semiconductor memory device according to claim 5, wherein said sense amplifier activating means includes:

a first section for selectively driving one of said sense amplifier activating signals to said power supply higher side potential;

a second section for selectively driving the one of said sense amplifier activating signals to said second potential;

a third section for driving the other of said sense amplifier activating signals to the ground potential; and

a fourth section for driving said sense amplifier activating signals to a precharge potential.

10. A method of accessing a semiconductor memory device, comprising the steps of:

selecting one of a plurality of word lines in response to a row address, wherein a memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells in each of rows of said matrix are connected to one of said plurality of word lines corresponding to the row;

driving, in response to a row address strobe signal, said selected word line to a potential which is higher by double of a threshold voltage of a MOS transistor than a power supply higher side potential at least momentarily;

reading a data from one memory cell as a selected memory cell connected to said selected word line and a selected one of a plurality of pairs of bit lines;

issuing sense amplifier activating signals in response to a sense control signal;

amplifying the data read from said selected memory cell onto the selected pair of bit lines in response to sense amplifier activating signals; and

selectively outputting the data on said selected pair of bit lines.

11. A method according to claim 10, further including:

rewriting the data read from said selected memory cell into said selected memory cell, and

wherein said driving step includes holding the potential of said selected word line to said first potential while said selected memory cell is accessed.

12. A method of accessing a semiconductor memory device, comprising the steps of:

selecting one of a plurality of word lines in response to a row address, wherein a memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells in each of rows of said matrix are connected to one of said plurality of word lines corresponding to the row;

driving, in response to a row address strobe signal, said selected word line to a first potential which is higher by a predetermined potential than a predetermined second potential, said second potential being higher than a power supply higher side potential;

reading a data from one memory cell as a selected memory cell connected to said selected word line and a selected one of a plurality of pairs of bit lines;

issuing sense amplifier activating signals in response to a sense control signal;

amplifying the data read from said selected memory cell onto the selected pair of bit lines in response to sense amplifier activating signals;

selectively outputting the data on said selected pair of bit lines;

rewriting the data read from said selected memory cell into said selected memory cell, wherein said driving step includes holding the potential of said selected word line to said first potential while said selected memory cell is accessed; and

wherein said issuing step includes issuing said sense amplifier activating signals for the rewrite operation into said selected memory cell in response to a sense control signal such that one of the bit lines of said selected pair is driven to said second potential.

13. A method of accessing a semiconductor memory device, comprising the steps of:

selecting one of a plurality of word lines in response to a row address, wherein a memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells in each of rows of said matrix are connected to one of said plurality of word lines corresponding to the row;

driving, in response to a row address strobe signal, said selected word line to a first potential which is higher by a predetermined potential than a predetermined second potential, said second potential being higher than a power supply higher side potential;

reading a data from one memory cell as a selected memory cell connected to said selected word line and a selected one of a plurality of pairs of bit lines;

issuing sense amplifier activating signals in response to a sense control signal;

amplifying the data read from said selected memory cell onto the selected pair of bit lines in response to sense amplifier activating signals;

selectively outputting the data on said selected pair of bit lines; and

rewriting the data read from said selected memory cell into said selected memory, and

wherein said driving step includes;

dropping the potential of said selected word line to a potential lower than said power supply higher side potential; and

driving the potential of said selected word line to said first potential for the rewrite operation.

14. A method according to claim 13, wherein said issuing step includes issuing said sense amplifier activating signals for the rewrite operation into said selected memory cell in response to a sense control signal such that one of the bit lines of said selected pair is driven to said second potential.

15. A method of accessing a semiconductor memory device, comprising the steps of:

selecting one of a plurality of word lines in response to a row address, wherein a memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells in each of rows of said matrix are connected to one of said plurality of word lines corresponding to the row;

driving, in response to a row address strobe signal, said selected word line to a potential which is higher than a predetermined second potential, said second potential being higher than a power supply higher side potential;

reading a data from one memory cell as a selected memory cell connected to said selected word line and a selected one of a plurality of pairs of bit lines;

issuing sense amplifier activating signals in response to a sense control signal;

amplifying the data read from said selected memory cell onto the selected pair of bit lines in response to sense amplifier activating signals;

selectively outputting the data on said selected pair of bit lines; and

dropping a supply voltage externally supplied, and wherein said second potential is a potential corresponding to said supply voltage externally supplied.

16. A method of accessing a semiconductor memory device, comprising the steps of:

selecting one of a plurality of word lines in response to a row address, wherein a memory cell array includes a plurality of memory cells arranged in a matrix, and the memory cells in each of rows of said matrix are connected to one of said plurality of word lines corresponding to the row;

driving, in response to a row address strobe signal, said selected word line to a potential which is higher than a predetermined second potential, said second potential being higher than a power supply higher side potential;

reading a data from one memory cell as a selected memory cell connected to said selected word line and a selected one of a plurality of pairs of bit lines;

issuing sense amplifier activating signals in response to a sense control signal;

amplifying the data read from said selected memory cell onto the selected pair of bit lines in response to sense amplifier activating signals;

selectively outputting the data on said selected pair of bit lines; and

boosting a supply voltage externally supplied, and

wherein said second potential is a potential corresponding to the boosted supply voltage.