Digital/analog bit synchronizer

• US 5,719,908 A
• Filed: 07/19/1995
• Issued: 02/17/1998
• Est. Priority Date: 07/19/1995
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Greeff, Roy Edgar, Arbanas, Glenn Arthur, Williams, Bruce Howard
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/503,953
• Time in Patent Office: 944 Days
• Field of Search: 375/327-328, 375/375-376, 331/14, 331/17, 331/18, 331/25, 331/1 A, 327/5, 327/12, 327/160, 327/163, 327/236
• US Class Current: 375/376
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/12 using a scanning signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

Claims

1. A high speed bit synchronizer for generating a coherent clock synchronized with a received digital data stream, comprising:

a digital phase detector having an input for receiving said digital data stream and producing a clocked data output,

first summing means having a first input coupled to the clocked data output of said digital phase detector,

offset eliminating means having an input coupled to the phase detector and a correction signal output coupled to a second input of said first summing means,

a loop filter,

said first summing means having positive inputs and a summed voltage output coupled to said loop filter,

a voltage controlled oscillator having an input coupled to the filtered summed voltage output and having the coherent clock with a steady state phase offset, and

the output of said first summing means having a linear output phase offset S-curve around the lock point of said phase detector, whereby seeking is substantially eliminated.

2. A high speed bit synchronizer as set forth in claim 1 which further includes a digital lock detector having an input coupled to said digital data stream and an output coupled to a second summing means,

said second summing means having a second input coupled to the output of said offset eliminating means,

a low pass filter having an input coupled to the output of said second summing means for producing an adjusted error signal output, and

a comparator coupled to receive said adjusted error signal output for producing a lock indication signal at the true lock point for said phase detector.

3. A high speed bit synchronizer as set forth in claim 1 wherein said digital phase detector comprises a flip-flop having a clocked data output coupled to a first exclusive OR gate,

said first exclusive OR gate having a second input coupled to said data stream and having a phase error signal output.

4. A high speed bit synchronizer as set forth in claim 3 wherein said digital phase detector further comprises a third summing means coupled to the first input of the first summing means and to said exclusive OR gate, and

the output of said offset eliminating means being coupled to the second input of said first summing means for producing a phase error correction signal adjusted for the occurrence of unsymmetrical data.

5. A high speed bit synchronizer as set forth in claim 4 wherein said offset eliminating means comprises a second flip-flop having a clocked data output and a clock data input, and

a second exclusive OR gate having an input coupled to the output of said second flip-flop for producing an offset correction signal.

6. A high speed bit synchronizer as set forth in claim 5 wherein said offset eliminating means further includes gating means coupled to the second exclusive OR gate, and

fourth summing means coupled to the output of said gating means for producing said correction signal output at the output of said offset eliminating means.

7. A high speed bit synchronizer as set forth in claim 1 wherein said digital phase detector comprises a third summing means coupled to said first summing means which comprises a digital summing circuit for producing a digital adjusted phase error signal, and

wherein said voltage control oscillator comprises a digital voltage controlled oscillator coupled to the output of said digital summing circuit.

8. A high speed bit synchronizer as set forth in claim 7 wherein said offset eliminating means comprises a high-low digital counter having a digital output coupled to an input of said digital summing circuit.

9. A high speed bit synchronizer as set forth in claim 1 which further comprises lock detector means coupled to the coherent clock and to said digital data stream for indicating a true lock point on said phase offset S-curve.

10. A high speed bit synchronizer as set forth in claim 9 wherein said lock detector means comprises a fifth summing means coupled to said second summing means.

11. A high speed bit synchronizer as set forth in claim 10 wherein said lock detector means further comprises a third flip-flop coupled to a third exclusive OR gate having an output coupled to said fifth summing means.