Expert system inference circuit

• US 5,720,006 A
• Filed: 09/14/1995
• Issued: 02/17/1998
• Est. Priority Date: 02/25/1993
• Status: Expired due to Fees

• Current Assignee: Reticular Systems Incorporated
• Original Assignee: Reticular Systems Incorporated
• Inventors: Ballard, Dan
• Primary Examiner(s): Downs, Robert W.
• Application Number:
  US08/528,310
• Time in Patent Office: 887 Days
• Field of Search: 395/64, 395/61, 395/51, 395/52
• US Class Current: 706/47
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06N 5/04 Inference or reasoning models
• CPC Class Codes: G06N 5/046 Forward inferencing; Production systems
• CPC Class Codes: G06N 5/047 Pattern matching networks; Rete networks
• CPC Class Codes: Y10S 706/916 Electronic or computer, internal or network, circuit

Abstract

A rule based processing system that is optimized for implementation in hardware. The system includes a set of logic gates that are used to implement a rule network connected to a working memory composed from a set of memory components. When a set of inputs are presented to the logic gates, a set of inferences are formed and the results are stored in the memory components. The inferences that are stored in the working memory are used to determine the state of the system at any given time. These inferences can be output to an external device to report on the status of the system. The rule based production system is designed to be implementable on a high performance semiconductor micro-chip and is thus suitable for use in embedded real-time applications.

Claims

1. An inference circuit, comprising:

a plurality of programmable function units representative of a rule network, each unit receiving a plurality of system condition signals and generating an action signal indicative of assertion or deassertion; and

a working memory comprising a plurality of working memory elements wherein each element receives and stores the action signal for a selected one of the units.

2. The inference circuit defined in claim 1, wherein each function unit comprises a static RAM.

3. The inference circuit defined in claim 2, wherein each memory element comprises a flip-flop.

4. The inference circuit defined in claim 1, wherein system condition signals or programmable signals are received by a tristate buffer in the programmable function unit and selectively fed to a RAM.

5. In an inference circuit having a plurality of programmable function units representative of a rule network and a working memory comprising a plurality of working memory elements, a method of inferencing, comprising the steps of:

receiving a plurality of system condition signals at each programmable function unit;

generating an action signal indicative of assertion or deassertion; and

receiving and storing in a working memory element the action signal for a selected one of the units.