Method and apparatus for testing memory devices and displaying results of such tests

• US 5,720,031 A
• Filed: 12/04/1995
• Issued: 02/17/1998
• Est. Priority Date: 12/04/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lindsay, Brent
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Palys, Joseph E.
• Application Number:
  US08/567,069
• Time in Patent Office: 806 Days
• Field of Search: 395/183.18, 395/185.1, 395/185.01, 395/183.22, 395/185.06, 395/185.07, 371/21.1, 371/21.2, 371/21.3, 371/21.5, 371/21.6, 365/200, 365/201
• US Class Current: 714/42
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

An apparatus and method for testing a semiconductor device allows error data to be displayed, in real time, based on the physical locations of the errors on the semiconductor device. A mapping circuit includes a router circuit, an error catch memory, and a topological circuit. The router circuit converts logical addresses employed by the semiconductor device to physical addresses employed by the error catch memory so that error data is appropriately routed from locations in the semiconductor device to corresponding locations in the error catch memory. The topological circuit then converts the physical addresses of the error data in the error catch memory to spatial addresses for allowing a host computer to rapidly display such errors as a bit map display on a visual display device. The router and topological circuits are preferably field programmable gate arrays or programmable read only memories so that the host computer can reprogram them for different semiconductor devices to be tested.

Claims

1. In a testing system for testing a semiconductor memory device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of memory locations each addressable by logical addresses, the apparatus comprising:

an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data written to the plurality of memory locations in the semiconductor device and data read from the plurality of memory locations, each memory cell of the error catch memory being addressable by a physical address;

a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of memory locations in the semiconductor device to selected memory cells in the error catch memory; and

a programmable topological circuit coupled to error catch memory and the computer, the programmable topological circuit receiving spatial addresses from the computer, converting selected spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses to the computer in response to the spatial addresses to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.

2. The apparatus of claim 1 wherein the programmable router circuit is a field programmable gate array.

3. The apparatus of claim 2 wherein the programmable router circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the memory locations in the semiconductor memory device.

4. The apparatus of claim 1 wherein the programmable topological circuit is a field programmable gate array.

5. The apparatus of claim 2 wherein the programmable topological circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the plurality of memory cells in the error catch memory.

6. The apparatus of claim 1 wherein the programmable router circuit is a programmable read only memory that stores a look-up table for converting the logical addresses to physical addresses.

7. The apparatus of claim 1 wherein topological circuit is a programmable read only memory that stores a look-up table for converting spatial addresses to physical addresses.

8. A method of testing a semiconductor memory device and displaying on a display device spatial locations of errors in the semiconductor device, the semiconductor device having a plurality of memory locations each addressable by logical row and column address signals, the method comprising the steps of:

loading a routing routine into a routing circuit for converting the logical addresses of the semiconductor device to physical addresses, the routing routine being based on a layout of the memory locations in the semiconductor memory device;

loading a mapping routine into a topological circuit for converting spatial addresses to physical addresses, the mapping routine being based on a layout of a plurality of memory cells in a error catch memory;

continually applying a test pattern to the semiconductor device, determining error data from the semiconductor device and routing the error data to the error catch memory based on the routing routine; and

substantially simultaneous with the step of continually applying a test pattern, constantly reading the error data from the error catch memory and displaying the error data at spatial locations on the display device based on the mapping routine.

9. The method of claim 8, further comprising the steps of:

determining a pattern for the row and column addresses of the memory locations in the semiconductor memory device, and

determining an optimal routing routine for converting the logical addresses of the semiconductor device to physical addresses based on the pattern for the row and column addresses of the memory locations in the semiconductor memory device.

10. The method of claim 8, further comprising the steps of:

determining a pattern for the row and column addresses of the memory cells in the error catch memory, and

determining an optimal mapping routine for mapping the spatial addresses to physical addresses based on the pattern for the row and column addresses of the memory cells in the error catch memory.

11. The method of claim 8 wherein the step of loading a routing routine into a routing circuit loads a routine into a field programmable gate array.

12. The method of claim 8 wherein the step of loading a mapping routine into a topological circuit loads a routine into a field programmable gate array.

13. The method of claim 8 wherein the step of loading a routing routine into a routing circuit loads a routine into a read only memory that stores a look-up table for converting the logical addresses to physical addresses.

14. The method of claim 8 wherein the step of loading a mapping routine into a topological circuit loads a routine into a read only memory that stores a look-up table for converting spatial addresses to physical addresses.

15. In a testing system for testing a semiconductor device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of circuit locations each addressable by logical addresses, the apparatus comprising:

an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data applied to the plurality of circuit locations in the semiconductor device and data read from the plurality of circuit locations, each memory cell of the error catch memory being addressable by a physical address; and

a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of circuit locations in the semiconductor device to selected memory cells in the error catch memory,

the error catch memory providing error data corresponding to selected physical addresses to the computer in response to spatial addresses from the computer to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.

16. A testing apparatus for testing a semiconductor device formed on a wafer, the semiconductor device having a plurality of memory circuits addressable by predetermined logical addresses, the apparatus comprising:

a computer having a display device, the computer capable of having test data written to, and data read from, the plurality of memory circuits in the semiconductor device based on the predetermined logical addresses;

an interface circuit for intercoupling to the semiconductor device and the computer;

a comparator circuit coupled to the semiconductor device for comparing the test data written to the plurality of memory circuits to the data read from the plurality of memory circuits and producing error data in response to such comparison, the computer capable of displaying the error data at predetermined spatial addresses on the display device; and

a mapping circuit having

an error catch memory having a plurality of memory cells for storing the error data, the plurality of memory cells being addressable by physical addresses,

a programmable router circuit coupled between the computer and the comparator circuit, and the error catch memory, the programmable router circuit converting the logical addresses to physical addresses to thereby route the error data to selected memory cells in the error catch memory, and

a programmable topological circuit coupled between the computer and the error catch memory for converting the physical addresses to spatial addresses to thereby allow the error data to map to spatial addresses on the display device.

17. The testing apparatus of claim 16, further comprising:

a test bed for releasable securing the wafer; and

a plurality of test probes for electrically intercoupling between the device and the interface circuit.

18. The testing apparatus of claim 16, further comprising an optical inspection device positioned over the test bed for allowing optical inspection of an upper surface of the wafer.

19. The apparatus of claim 16 wherein the programmable router circuit is a field programmable gate array.

20. The apparatus of claim 16 wherein the programmable router circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the memory circuits in the semiconductor memory device.

21. The apparatus of claim 16 wherein the programmable topological circuit is a field programmable gate array.

22. The apparatus of claim 16 wherein the programmable topological circuit is a field programmable gate array, and wherein the field programmable gate array is programmable by the computer based on a layout of the plurality of memory cells in the error catch memory.

23. The apparatus of claim 16 wherein the programmable router circuit is a programmable read only memory that stores a look-up table for converting the logical addresses to physical addresses.

24. The apparatus of claim 16 wherein topological circuit is a programmable read only memory that stores a look-up table for converting spatial addresses to physical addresses.