Method and apparatus for testing memory devices and displaying results of such tests
First Claim
1. In a testing system for testing a semiconductor memory device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of memory locations each addressable by logical addresses, the apparatus comprising:
- an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data written to the plurality of memory locations in the semiconductor device and data read from the plurality of memory locations, each memory cell of the error catch memory being addressable by a physical address;
a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of memory locations in the semiconductor device to selected memory cells in the error catch memory; and
a programmable topological circuit coupled to error catch memory and the computer, the programmable topological circuit receiving spatial addresses from the computer, converting selected spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses to the computer in response to the spatial addresses to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.
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Accused Products
Abstract
An apparatus and method for testing a semiconductor device allows error data to be displayed, in real time, based on the physical locations of the errors on the semiconductor device. A mapping circuit includes a router circuit, an error catch memory, and a topological circuit. The router circuit converts logical addresses employed by the semiconductor device to physical addresses employed by the error catch memory so that error data is appropriately routed from locations in the semiconductor device to corresponding locations in the error catch memory. The topological circuit then converts the physical addresses of the error data in the error catch memory to spatial addresses for allowing a host computer to rapidly display such errors as a bit map display on a visual display device. The router and topological circuits are preferably field programmable gate arrays or programmable read only memories so that the host computer can reprogram them for different semiconductor devices to be tested.
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Citations
24 Claims
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1. In a testing system for testing a semiconductor memory device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of memory locations each addressable by logical addresses, the apparatus comprising:
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an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data written to the plurality of memory locations in the semiconductor device and data read from the plurality of memory locations, each memory cell of the error catch memory being addressable by a physical address; a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of memory locations in the semiconductor device to selected memory cells in the error catch memory; and a programmable topological circuit coupled to error catch memory and the computer, the programmable topological circuit receiving spatial addresses from the computer, converting selected spatial addresses to selected physical addresses, and providing error data corresponding to the selected physical addresses to the computer in response to the spatial addresses to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of testing a semiconductor memory device and displaying on a display device spatial locations of errors in the semiconductor device, the semiconductor device having a plurality of memory locations each addressable by logical row and column address signals, the method comprising the steps of:
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loading a routing routine into a routing circuit for converting the logical addresses of the semiconductor device to physical addresses, the routing routine being based on a layout of the memory locations in the semiconductor memory device; loading a mapping routine into a topological circuit for converting spatial addresses to physical addresses, the mapping routine being based on a layout of a plurality of memory cells in a error catch memory; continually applying a test pattern to the semiconductor device, determining error data from the semiconductor device and routing the error data to the error catch memory based on the routing routine; and substantially simultaneous with the step of continually applying a test pattern, constantly reading the error data from the error catch memory and displaying the error data at spatial locations on the display device based on the mapping routine. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. In a testing system for testing a semiconductor device, the testing system having a computer and a visual display device, an apparatus for assisting in the display of locations of errors in the semiconductor device on the display device, the semiconductor device having a plurality of circuit locations each addressable by logical addresses, the apparatus comprising:
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an error catch memory having a plurality of memory cells for storing error data, the error data corresponding to a comparison between data applied to the plurality of circuit locations in the semiconductor device and data read from the plurality of circuit locations, each memory cell of the error catch memory being addressable by a physical address; and a programmable router circuit coupled to the error catch memory and the semiconductor device, the programmable router circuit converting the logical addresses to physical addresses to thereby route for storage the error data from the plurality of circuit locations in the semiconductor device to selected memory cells in the error catch memory, the error catch memory providing error data corresponding to selected physical addresses to the computer in response to spatial addresses from the computer to thereby allow the error data from the semiconductor device to map to spatial addresses on the display device for displaying the locations of errors in the semiconductor device.
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16. A testing apparatus for testing a semiconductor device formed on a wafer, the semiconductor device having a plurality of memory circuits addressable by predetermined logical addresses, the apparatus comprising:
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a computer having a display device, the computer capable of having test data written to, and data read from, the plurality of memory circuits in the semiconductor device based on the predetermined logical addresses; an interface circuit for intercoupling to the semiconductor device and the computer; a comparator circuit coupled to the semiconductor device for comparing the test data written to the plurality of memory circuits to the data read from the plurality of memory circuits and producing error data in response to such comparison, the computer capable of displaying the error data at predetermined spatial addresses on the display device; and a mapping circuit having an error catch memory having a plurality of memory cells for storing the error data, the plurality of memory cells being addressable by physical addresses, a programmable router circuit coupled between the computer and the comparator circuit, and the error catch memory, the programmable router circuit converting the logical addresses to physical addresses to thereby route the error data to selected memory cells in the error catch memory, and a programmable topological circuit coupled between the computer and the error catch memory for converting the physical addresses to spatial addresses to thereby allow the error data to map to spatial addresses on the display device. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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Specification