Method for manufacturing MOS type semiconductor device

• US 5,721,148 A
• Filed: 12/03/1996
• Issued: 02/24/1998
• Est. Priority Date: 12/07/1995
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Nishimura, Takeyoshi
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/759,943
• Time in Patent Office: 448 Days
• Field of Search: 437/40, 437/41, 437/52, 437/203, 148/DIG. 126
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

In a method for manufacturing a MOS type semiconductor device, a first conductivity type layer is formed in a surface layer of a second conductivity type base region on a first conductivity type drain layer, a gate trench is formed in the base region, and a gate electrode is then formed in the gate trench through a gate insulation film. An exposed surface of the obtained structure is covered with an inter-layer insulation film, and a source contact trench that reaches inside the second conductivity type base region is formed through the inter-layer insulation film and first conductivity type layer while a gate contact trench that reaches inside the gate electrode is formed through the inter-layer insulation film. A portion of the inter-layer insulation film and the source contact trench are covered with a first metal film that forms a source electrode, and another portion of the inter-layer insulation film and the gate contact trench are covered with a second metal film that forms a gate metal electrode.

Claims

1. A method for manufacturing a MOS type semiconductor device, comprising the steps of:

forming a first conductivity type layer in a surface layer of a second conductivity type base region on a first conductivity type drain layer;

forming a gate trench;

forming a gate electrode in said gate trench on a gate insulation film;

covering an exposed surface of said first conductivity type layer and said gate electrode with an inter-layer insulation film, and dividing the inter-layer insulation film and the first conductivity type layer so as to concurrently form a source contact trench that reaches inside said second conductivity type base region, and a gate contact trench that extends through said inter-layer insulation film and reaches inside said gate electrode; and

covering a first portion of said inter-layer insulation film and said source contact trench with a first metal film so as to form a source electrode, and covering a second portion of said inter-layer insulation film and said gate contact trench with a second metal film so as to form a gate metal electrode.

2. A method for manufacturing a MOS type semiconductor device, comprising the steps of:

forming a second conductivity type base region on a first conductivity drain layer with an insulating film formed as a surface layer of the second conductivity type base region;

leaving a part of said insulating film on said second conductivity type base region;

forming first conductivity type source regions such that said insulating film is used as a mask for forming the source regions;

forming a gate trench;

forming a gate electrode in said gate trench on a gate insulation film;

covering exposed surfaces of said first conductivity type source regions and said gate electrode with an inter-layer insulation film, forming a first hole through the inter-layer insulation film, and removing said part of said insulating film to form a second hole through the inter-layer insulation film; and

forming a gate metal electrode and a source electrode such that the gate metal electrode is in contact with said gate electrode through said first hole, and such that the source electrode is in contact with said second conductivity type base region and said first conductivity type source region through said second hole.

3. A method for manufacturing a MOS type semiconductor device, comprising the steps of:

forming a gate trench that extends from a surface of a second conductivity type base region formed on a first conductivity type drain layer;

forming an insulating film on a surface of said second conductivity base region and in said gate trench, and then forming a conductive film on the insulating film;

leaving a first part of said insulating film and said conductive film on said surface of said base region, and a second part of the insulating film and the conductive film that is located in said gate trench, while removing a remaining part of the insulating film and the conductive film;

forming first conductivity type source regions in a surface layer of said second conductivity type base region, and covering exposed surfaces of said first conductivity type source regions and remaining parts of said conductive film with an inter-layer insulation film;

forming a first hole through the inter-layer insulation film, and removing said first part of said insulating film and said conductive film left on said base region to form a second hole through the inter-layer insulation film; and

forming a gate metal electrode and a source electrode such that the gate metal electrode is in contact with said gate electrode through said first hole and the source electrode is in contact with said second conductivity type base region and said first conductivity type source region through said second hole.