Method of manufacture of thin film transistor SRAM device with a titanium nitride or silicide gate

• US 5,721,163 A
• Filed: 06/10/1996
• Issued: 02/24/1998
• Est. Priority Date: 06/10/1996
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Inventors: Sundaresan, Ravishankar
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/661,252
• Time in Patent Office: 624 Days
• Field of Search: 437/21, 437/40 TFI, 437/40 GS, 437/41 TFI, 437/41 GS, 437/45, 437/52, 437/57, 437/59, 437/192, 437/200, 438/152, 438/153, 438/158, 438/159, 438/291
• US Class Current: 438/153
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer. The second end of the first region is apart from the second side surface of the control gate electrode by a distance more than a thickness of a part of the second insulating layer covering a side surface of the control gate electrode and does not overlap with the control gate electrode, wherein the second and third regions serve as a source and a drain of the thin film field effect transistor, respectively.

Claims

1. A method of forming a device including a thin film field effect transistor and a buried contact on a doped silicon semiconductor substrate of a first conductivity type;

forming source/drain regions of a field effect transistor in said substrate,

forming a first insulating layer over said semiconductor substrate;

forming a buried contact via opening through said first insulating layer to expose said source/drain region in said doped silicon semiconductor substrate,

forming a conductor layer providing a combined buried contact and gate electrode for a thin film field effect transistor on said first insulating layer composed of a material selected from the group consisting of titanium nitride and a refractory metal silicide over said first insulating layer,

forming a second insulating layer covering an upper surface and first and second side surfaces of said gate electrode, and

forming a polycrystalline silicon film on said semiconductor substrate over said first and second insulating layers, performing a threshold implanting step doping said polysilicon film with dopant of a second conductivity type opposite from said first conductivity type,

forming a mask above said gate electrode over a first region of said semiconductor film,

performing ion implanting of dopant of said first conductivity type into said semiconductor film aside from said mask to form a second region of said semiconductor film of said first conductivity type formed in contact with a first end of said first region, and a third region of said semiconductor film of said first conductivity type and formed in contact with a second end of said first region, said gate electrode and a part of said first region being overlapped with each other over said second insulating layer,

said first region forming the channel of a thin film transistor and the width of said first region being shorter than the width of said gate electrode, wherein said second region and said third region serve as a source and a drain of said thin film field effect transistor, respectively.

2. A method of forming a semiconductor device according to claim 1, in which said first conductivity type is a P type and said second conductivity type is an N type.

3. A method of forming a semiconductor device according to claim 1, in which said first conductivity type is a P type and said second conductivity type is an N type,

said polycrystalline silicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3

said second and third regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.

4. A method of forming a semiconductor device according to claim 1 wherein:

said polycrystalline silicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

said second and third regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.

5. A method of forming a semiconductor device according to claim 1 wherein:

said first insulating layer has a thickness from about 500 Å

to about 1,000 Å

,

said conductor layer has a thickness from about 500 Å

to about 1,000 Å

,

said polycrystalline silicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

said second and third regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.

6. A method of forming an SRAM device including a thin film field effect transistor and a buried contact on a doped silicon semiconductor substrate of a first conductivity type;

forming conventional N+ and P+ source/drain regions of a field effect transistor in said substrate, a gate oxide layer over said substrate and a gate electrode over said substrate to form FET devices,

deposition of an interconductor dielectric layer over said FET devices,

forming a buried contact via opening through said interconductor dielectric layer to said drain region in said doped silicon semiconductor substrate,

depositing a refractory metal silicide gate electrode layer to form a buried contact in said via opening to said drain region and for forming a gate electrode for another field effect transistor ,

formation of mask over said gate layer and patterning said gate layer by etching of said gate electrode layer to form a gate electrode with exposed surfaces,

forming a thin film transistor gate oxide layer covering said exposed surfaces of said gate electrode layer,

depositing an undoped semiconductor polysilicon thin film for a thin film transistor active channel over said gate oxide layer,

performing a Vt implant adjustment of said polysilicon thin film by implanting therein a dopant selected from the group consisting of boron and phosphorus dopant with dopant ions in a dose of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

forming thin film transistor source/drain regions in said polysilicon thin film.

7. A method of forming a semiconductor device according to claim 6 wherein:

said polysilicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

said source/drain regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.

8. A method of forming a semiconductor device according to claim 6 wherein:

said interconductor dielectric layer has a thickness from about 500 Å

to about 1,000 Å

,

said conductor layer has a thickness from about 500 Å

to about 1,000 Å

,

said polysilicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

said source/drain regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.

9. A method of forming an SRAM device including a thin film field effect transistor and a buried contact on a doped silicon semiconductor substrate of a first conductivity type;

forming conventional N+ and P+ source/drain regions of a field effect transistor in said substrate, a gate oxide layer over said substrate and a gate electrode over said substrate to form FET devices,

deposition of an interconductor dielectric layer over said FET devices,

forming a buried contact via opening through said interconductor dielectric layer to said drain region in said doped silicon semiconductor substrate,

depositing a TiN gate electrode layer to form a buried contact in said via opening to said drain region,

formation of mask over said gate electrode layer and patterning said gate layer by etching of a gate electrode to form a gate electrode with exposed surfaces,

forming a thin film transistor gate oxide layer covering said exposed surfaces of said gate electrode,

depositing an undoped semiconductor polysilicon thin film for a thin film transistor active channel over said gate oxide layer,

performing a Vt implant adjustment of said polysilicon thin film by implanting therein a dopant selected from the group consisting of boron and phosphorus dopant with dopant ions in a dose of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

forming thin film transistor source/drain regions in said polysilicon thin film.

10. A method of forming a semiconductor device according to claim 9 wherein:

said polysilicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

said source/drain regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.

11. A method of forming a semiconductor device according to claim 9 wherein:

said interconductor dielectric layer has a thickness from about 500 Å

to about 1,000 Å

,

said conductor layer has a thickness from about 500 Å

to about 1,000 Å

,

said polysilicon film has a thickness from about 300 Å

to about 800 Å and

said film is doped by said dopant which is selected from the group consisting of boron and said threshold implant step provides a phosphorus dopant with dopant ions of from about 10¹⁶ atoms/cm3 to about 10¹⁷ atoms/cm3, and

said source/drain regions are doped with B¹¹ dopant with dopant ions of from about 10¹⁹ atoms/cm3 to about 10²⁰ atoms/cm3.