Process for forming a semiconductor device and a static-random-access memory cell
First Claim
1. A process for forming a semiconductor device comprising the steps of:
- forming a first conductive layer over a substrate having a first region and a second region;
forming a first dielectric layer over the first conductive layer;
selectively etching the first dielectric layer to form a patterned first dielectric layer, wherein;
a first portion of the first dielectric layer is removed over the first region of the substrate; and
a second portion of the first dielectric layer remains over the second region of the first conductive layer;
forming a second conductive layer over the patterned first dielectric layer and the first conductive layer; and
selectively etching the first conductive layer, the first dielectric layer, and the second conductive layer to form a first gate electrode and a second gate electrode, wherein;
the first gate electrode overlies the first region of the substrate and includes the first conductive layer and the second conductive layer; and
the second gate electrode overlies the second region of the substrate and includes the first conductive layer, the second portion of the first dielectric layer, and the second conductive layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.
-
Citations
13 Claims
-
1. A process for forming a semiconductor device comprising the steps of:
-
forming a first conductive layer over a substrate having a first region and a second region; forming a first dielectric layer over the first conductive layer; selectively etching the first dielectric layer to form a patterned first dielectric layer, wherein; a first portion of the first dielectric layer is removed over the first region of the substrate; and a second portion of the first dielectric layer remains over the second region of the first conductive layer; forming a second conductive layer over the patterned first dielectric layer and the first conductive layer; and selectively etching the first conductive layer, the first dielectric layer, and the second conductive layer to form a first gate electrode and a second gate electrode, wherein; the first gate electrode overlies the first region of the substrate and includes the first conductive layer and the second conductive layer; and the second gate electrode overlies the second region of the substrate and includes the first conductive layer, the second portion of the first dielectric layer, and the second conductive layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
Specification