Multiple storage planes read only memory integrated circuit device and method of manufacture thereof

• US 5,721,169 A
• Filed: 04/29/1996
• Issued: 02/24/1998
• Est. Priority Date: 04/29/1996
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Inventors: Lee, Bob Hsino-Lun
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/639,392
• Time in Patent Office: 666 Days
• Field of Search: 438/130, 438/275, 438/276, 438/277, 438/278, 438/290, 438/587, 438/588
• US Class Current: 438/278
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A ROM memory array comprises a doped silicon substrate having a surface with a first array of parallel bitlines formed in the substrate at the surface with an array of channel regions between the bitlines. A dielectric layer is formed on the substrate with a wordline array composed of transversely disposed parallel conductors formed on the dielectric layer, with the bitlines and the channel regions and the wordline array forming an array of field effect transistors. A gate oxide layer is formed over the wordlines. A thin film polysilicon storage plane is formed over the gate oxide layer with a second array of alternating parallel bitlines and channel regions formed in the thin film polysilicon storage plane. The second array of bitlines and channel regions is orthogonally disposed relative to the wordline array and the second array of bitlines is formed in a storage plane over an interpolysilicon oxide dielectric isolation layer. The wordline array and the second array of parallel bitlines and channel regions form an array of thin film transistors.

Claims

1. A method of manufacture of a ROM structure on a doped silicon semiconductor substrate having a surface, said method comprising said the steps as follows:

forming a dielectric layer on said surface of said substrate,

forming a first array of bitlines in said substrate at said surface below said dielectric layer,

forming a first parallel array of wordlines over said dielectric layer, said first array of wordlines being orthogonally oriented relative to said first array of bitlines,

forming a gate oxide layer covering said wordlines and exposed portions of said dielectric layer,

forming a first thin film polysilicon layer over said gate first dielectric layer comprising a second array of alternating parallel bitlines and channel regions, said second array of bitlines and channel regions being orthogonally disposed relative to said first wordline array.

2. A method in accordance with claim 1 wherein planarization of wordlines is achieved through formation of an oxide layer planarized by a method selected from the group consisting of an etchback process and a chemical mechanical polishing process.

3. A method in accordance with claim 1 wherein said wordlines are formed of polysilicon deposited by chemical vapor deposition followed by doping.

4. A method in accordance with claim 1 wherein said process of forming said gate oxide layer and said dielectric layer comprises thermal growth thereof.

5. A method in accordance with claim 1 wherein said process of forming said first thin film polysilicon layer over said dielectric layer comprises chemical vapor deposition.

6. A method in accordance with claim 2 wherein said wordlines are formed of polysilicon deposited by chemical vapor deposition followed by doping.

7. A method in accordance with claim 6 wherein said process of forming said gate oxide layer and said dielectric layer comprises thermally growth thereof.

8. A method in accordance with claim 7 wherein said process of forming said first thin film polysilicon layer over said dielectric layer comprises chemical vapor deposition.

9. A method in accordance with claim 1 wherein said steps are performed as follows:

an isolation dielectric layer is formed over said first thin film polysilicon layer,

forming a second thin film polysilicon layer over said isolation dielectric layer,

forming a third array of bitlines and channel regions in said second thin film polysilicon layer,

forming a second dielectric layer covering said second thin film polysilicon layer,

forming a second parallel array of wordlines over said second dielectric layer, said second array of wordlines being orthogonally oriented relative to said third array of bitlines,

forming a third dielectric layer covering said second array of wordlines and exposed portions of said second dielectric layer,

forming a third thin film polysilicon layer over said third dielectric layer, and

forming a fourth array of bitlines and channel regions in said third thin film polysilicon layer.

10. A method in accordance with claim 9 wherein planarization of wordlines is achieved through formation of an oxide layer planarized by a method selected from the group consisting of an etchback process and a chemical mechanical polishing process.

11. A method in accordance with claim 9 wherein said wordlines are formed of polysilicon deposited by chemical vapor deposition followed by doping.

12. A method in accordance with claim 9 wherein said process of forming said gate oxide layer and said dielectric layers comprises thermal growth thereof.

13. A method in accordance with claim 9 wherein said process of forming said thin film polysilicon layers comprises chemical vapor deposition.

14. A method in accordance with claim 10 wherein said wordlines are formed of polysilicon deposited by chemical vapor deposition followed by doping.

15. A method in accordance with claim 14 wherein said process of forming said gate oxide layer and said dielectric layers comprises thermal growth thereof.

16. A method in accordance with claim 15 wherein said process of forming said thin film polysilicon layers comprises chemical vapor deposition.

17. A method in accordance with claim 1 wherein said ROM code dopant comprises Boron.

18. A method in accordance with claim 9 wherein said ROM code dopant comprises Boron.

19. A method in accordance with claim 15 wherein said ROM code dopant comprises Boron.

20. A method in accordance with claim 16 wherein said ROM code dopant comprises Boron.