Block segmentation of configuration lines for fault tolerant programmable logic device
First Claim
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1. A programmable logic device (PLD) comprising:
- at least one control line for receiving at least one configuration data stream from a configuration data source;
a control bus for routing the at least one configuration data stream from the control line;
a plurality of programmable blocks;
a plurality of storage devices within each of said plurality of programmable blocks for receiving and storing configuration data;
a programming circuit within each of said plurality of programmable blocks coupled by programming lines to each of said plurality of storage devices, wherein each programming circuit couples only to the storage devices in the same block as the programming circuit;
at least one data line entering each of said plurality of programmable blocks from the control bus and coupled to the programming circuit for coupling the configuration data stream to the programming circuit, the configuration data stream selecting at least one of the plurality of programmable blocks independently of any remaining programmable blocks in said plurality of blocks.
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Abstract
A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided within each block. A block select line is coupled to each block such that when the block select is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.
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Citations
19 Claims
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1. A programmable logic device (PLD) comprising:
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at least one control line for receiving at least one configuration data stream from a configuration data source; a control bus for routing the at least one configuration data stream from the control line; a plurality of programmable blocks; a plurality of storage devices within each of said plurality of programmable blocks for receiving and storing configuration data; a programming circuit within each of said plurality of programmable blocks coupled by programming lines to each of said plurality of storage devices, wherein each programming circuit couples only to the storage devices in the same block as the programming circuit; at least one data line entering each of said plurality of programmable blocks from the control bus and coupled to the programming circuit for coupling the configuration data stream to the programming circuit, the configuration data stream selecting at least one of the plurality of programmable blocks independently of any remaining programmable blocks in said plurality of blocks. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A fault tolerant programmable logic device (PLD) on a single chip comprising:
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a plurality of programmable tiles organized in blocks wherein each block comprises a unique subset of the plurality of programmable tiles; a data bus extending to each of the blocks; independent address means for each block, the independent address means coupled to the data bus; a block enable line coupled to each block such that when the block enable line is asserted the address means of a selected block transfers data from the data bus to the unique subset of the plurality of programmable tiles in the selected block, and when the block enable line is deasserted the data bus is substantially electrically isolated from the independent address means of the selected block, the block enable lines coupled to the blocks being asserted and deasserted simultaneously so that any failed blocks are removed without affecting the operation of the remaining blocks on the single chip.
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8. A programmable device (PLD) comprising:
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an array of switches; a plurality of logical blocks, wherein each logical block comprises a unique subset of the array of switches; a block select bus for providing a block select signal to selected ones of the plurality of logical blocks; a row register within each logical block, the row register responsive to the block select signal and having a plurality of row select lines supplying a row select signal to selected ones of the array of switches; and a data register within each logical block, the data register responsive to the block select signal and having a plurality of column lines supplying data to the selected ones of the array of switches. - View Dependent Claims (9, 10)
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11. A programmable logic device (PLD) having a plurality of programmable logic blocks, each programmable logic block comprising:
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a plurality of storage devices for receiving and storing configuration data; a block enable line for receiving a block enable signal; at least one data line for supplying configuration data; a data register coupled to the at least one data line and responsive to the block enable signal for temporarily storing a portion of the configuration data; and an address circuit coupled to the at least one data line and responsive to the block enable signal for causing a selected number of the plurality of storage devices in the block to store the portion of configuration data from the data register.
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12. A programmable logic device (PLD) having a plurality of programmable logic blocks, each programmable logic block comprising:
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a plurality of storage devices for receiving and storing configuration data; a block enable line for receiving a block enable signal; at least one data line for supplying configuration data; a data register coupled to the at least one data line and responsive to the block enable signal for temporarily storing a portion of the configuration data; and an address circuit coupled to the at least one data line and responsive to the block enable signal for causing a selected number of the plurality of storage devices in the block to store the portion of configuration data from the data register; a first clock line; a second clock line; a first AND gate receiving the first clock line and the block enable signal, the first AND gate generating a first gated clock signal; a second AND gate receiving the second clock line and the block enable signal, the second AND gate generating a second gated clock signal; said data register comprising; (a) a first shift register having a data input coupled to the at least one data line and having a first clock input receiving the first gated clock signal; (b) a plurality of address lines extending from each bit of the first shift register and terminating at the width of the programmable logic block; (c) a second shift register having a data input coupled to the at least one data line and having a second clock input receiving the second gated clock signal; (d) a plurality of column lines extending from each bit of the second shift register and terminating at the length of the programmable logic block.
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13. A programmable logic device (PLD) comprising:
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a plurality of programmable tiles, each tile comprising a plurality of programmable storage devices; a plurality of logic blocks, wherein each logic block comprises a unique set of the programmable tiles; a first clock line coupled to each logic block; a second clock line coupled to each logic block; a data line coupled to each logic block; a plurality of block select lines wherein each of the plurality of block select lines is coupled to only one logic block; and an address circuit within each logic block responsive to the first clock line, the second clock line, the data line, and the block select line, wherein the address circuit has a plurality of address lines extending only to each of the programmable tiles within the logic block, the address circuit capable of storing data received from the data line when a preselected signal is received on the block select line. - View Dependent Claims (14)
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15. A method for loading a configuration data stream into a programmable logic device having a plurality of fault tolerant blocks on a single chip with each block having a plurality of storage devices, the method comprising the steps of:
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selecting at least one block of storage devices of the programmable logic device independently of any remaining blocks in said plurality of blocks so that if any of the plurality of blocks are faulty the remaining blocks on the single chip can be selected; addressing selected storage devices within the at least one selected block; loading a portion of the configuration data stream into the addressed storage devices; and repeating the selecting, addressing, and loading steps until the configuration data stream is exhausted. - View Dependent Claims (16, 17, 18, 19)
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Specification