Electrostatc discharge protection network

• US 5,721,656 A
• Filed: 06/10/1996
• Issued: 02/24/1998
• Est. Priority Date: 06/10/1996
• Status: Expired due to Fees

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Ker, Ming-Dou, Wu, Chau-Neng
• Primary Examiner(s): Young, Brian K.
• Assistant Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US08/661,105
• Time in Patent Office: 624 Days
• Field of Search: 361/56, 361/111, 361/91, 256/355-363
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An electrostatic discharge protection network which diverts ESD stress arising between any two contact pads of an IC device, in order to prevent damage to the internal circuitry of the IC device. An ESD discharge bus is arranged around the periphery of an IC chip. Between each IC pad and the discharge bus, there is a protection circuit to directly bypass an ESD stress arising at any two IC pads. Each ESD protection circuit includes a diode, a thick-oxide device, a resistor, and a capacitor. The protection circuit is operated in snapback mode without causing breakdown. Therefore, the triggering voltage of the ESD protection circuit is lowered to the level of the snapback voltage but not to the level of the breakdown voltage.

Claims

1. An electrostatic discharge protection network for protecting a circuit internal to an IC from ESD damage, comprising:

a conducting line;

a plurality of IC contact pads for electrical coupling to the internal circuit;

a plurality of protection circuits, each of the protection circuits being electrically coupled between a corresponding one of the contact pads and the conducting line, each of the protection circuits comprising;

a thick-oxide device having a bulk terminal, a drain terminal coupled to the corresponding contact pad, a source terminal coupled to the conducting line, and a gate terminal coupled to the drain terminal;

a resistor coupled between the bulk terminal and the conducting line;

a capacitor coupled between the corresponding contact pad and the bulk terminal; and

a diode having an anode coupled to the conducting line and a cathode coupled to the corresponding contact pad.

2. The protection network as claimed in claim 1, wherein at least one of the contact pads is an input pad.

3. The protection network as claimed in claim 1, wherein at least one of the contact pads is an output pad.

4. The protection network as claimed in claim 1, wherein at least one of the contact pads is an input/output pad.

5. The protection network as claimed in claim 1, wherein at least one of the contact pads is a power pad.

6. The protection network as claimed in claim 1, further comprising:

an N-type silicon substrate, wherein the thick oxide device is formed on the substrate;

a P-well formed in the substrate;

at least one contact region formed in the P-well;

an isolating structure formed on the substrate;

a polysilicon layer formed on the isolating structure, the polysilicon layer being coupled to the contact region and being coupled by the resistor to the conducting line;

a dielectric layer overlying the polysilicon layer;

a metal pad formed on the dielectric layer above the polysilicon layer, wherein the metal pad, the dielectric layer, and the polysilicon layer form the capacitor, and wherein the capacitor couples an ESD voltage to the P-well when an ESD stress arises at the metal pad;

a first heavily-doped N-type region formed in the P-well and coupled to the metal pad; and

at least one second heavily-doped N-type region spaced apart from the first heavily-doped N-type region, and coupled to the conducting line, wherein the first heavily-doped N-type region, the second heavily-doped N-type region, and the P-well form a bipolar junction transistor which bypasses ESD stress when the ESD voltage is coupled to the P-well through the capacitor.