Control gate driver circuit for a non-volatile memory and memory using same

• US 5,721,704 A
• Filed: 08/23/1996
• Issued: 02/24/1998
• Est. Priority Date: 08/23/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Morton, Bruce L.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/703,174
• Time in Patent Office: 550 Days
• Field of Search: 365/185.05, 365/185.18, 365/185.23, 365/185.26, 365/185.27, 365/185.29, 365/185.33, 365/218, 365/226
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.

Claims

1. A control gate driver circuit for providing a predetermined voltage to a control gate of an erasable programmable non-volatile memory cell during a read mode thereof, comprising:

a pass transistor of a predetermined conductivity type having a gate electrode coupled to a first voltage reference terminal, a first current electrode, a second current electrode coupled to the control gate, and a bulk electrode coupled to the first current electrode; and

a bias circuit having an output terminal coupled to the first current electrode of the pass transistor, wherein the bias circuit generates the predetermined voltage on the output terminal, wherein the predetermined voltage is substantially equal to a threshold voltage of the pass transistor plus an incremental voltage.

2. The control gate driver circuit of claim 1, wherein the bias circuit further comprises:

a bias transistor of the predetermined conductivity type of the pass transistor having a gate electrode coupled to the first voltage reference terminal, a first current electrode coupled to the output terminal, a second current electrode coupled to the first voltage reference terminal, and a bulk electrode; and

a bulk bias circuit having a first voltage terminal coupled to the first current electrode of the bias transistor, and a second voltage electrode coupled to the bulk electrode of the bias transistor, wherein the bulk bias circuit produces a higher voltage potential at the second voltage electrode than at the first voltage reference terminal.

3. The control gate driver circuit of claim 2, wherein the bias transistor is substantially similar to the pass transistor.

4. The control gate driver circuit of claim 2, wherein the bulk bias circuit comprises:

a first voltage drop device having a first terminal coupled to a second voltage reference terminal and a second terminal coupled to the bulk electrode; and

a second voltage drop device having a first terminal coupled to the second terminal of the first voltage drop device, and a second terminal coupled to the first current electrode of the bias transistor.

5. The control gate driver circuit of claim 4, wherein the first voltage drop device and the second voltage drop device are resistors.

6. The control gate driver circuit of claim 4, wherein the predetermined voltage is greater than approximately 100 millivolts.

7. The control gate driver circuit of claim 1 further comprising:

an isolation circuit having an input terminal coupled to the output terminal of the bias circuit, an output terminal coupled to the first current electrode of the pass transistor, and a control electrode for receiving a control signal which enables the isolation circuit.

8. The control gate driver circuit of claim 1, wherein the predetermined conductivity type is a p-channel transistor.

9. A control gate driver circuit for providing a predetermined voltage to a control gate of an erasable programmable non-volatile memory cell during a program mode thereof, comprising:

a first program voltage source having a reference terminal for providing a first programming voltage;

a first pass transistor of a predetermined conductivity type having a control electrode, a first current electrode coupled to the reference terminal, and a second current electrode for driving the control gate;

a pulsing circuit having a pulsed output terminal coupled to the control electrode of the first pass transistor, and a data input, for receiving at least one data signal, wherein the pulsing circuit provides a pulsed representation of the at least one data signal at the pulsed output terminal; and

a decoder having an address input for receiving an address signal, and a decoded output coupled to the data input of the pulsing circuit, wherein the decoder decodes the address input during the program mode.

10. The control gate driver circuit of claim 9, wherein the pulsing circuit further comprises a clock input for receiving a clock signal, wherein the pulsed representation of the at least one data signal is based on the clock signal.

11. The control gate driver circuit of claim 9, further comprising:

a second pass transistor having a control electrode coupled to the pulsed output terminal, a first current electrode coupled to the second current electrode of the first pass transistor, and a second current electrode for driving the control gate.

12. The control gate driver circuit of claim 9, further comprising:

a second program voltage source having a reference terminal for providing a second programming voltage; and

a second pass transistor of the predetermined conductivity type having a gate elect-rode coupled to a first voltage reference terminal, a first current electrode coupled to the reference terminal of the second program voltage source, and a second current electrode coupled to the control gate.

13. The control gate driver circuit of claim 12 wherein the first program voltage is a negative voltage, and the second program voltage is a non-negative voltage.

14. The control gate driver circuit of claim 12, further comprising:

an isolation circuit having an input terminal coupled to the reference terminal of the second program voltage source, an output electrode coupled to the first current electrode of the second pass transistor, and a control electrode for receiving a control signal which enables the isolation circuit during the program mode.

15. The control gate driver circuit of claim 14 wherein the first programming voltage is provided to the control circuit when the memory cell is selected for programming, and the second programming voltage is provided to the control gate when the memory cell is not selected for programming.

16. A control gate driver circuit having a control gate voltage terminal for providing a control gate voltage to the control gate of an erasable programmable non-volatile memory cell, the circuit comprising:

a read voltage terminal;

an erase voltage terminal;

a program select voltage terminal;

a program non-select voltage terminal;

a first decode portion for receiving an address and control signals, and coupled to the read voltage terminal, the erase voltage terminal, and the program non-select voltage terminal, and having a first voltage output, the first decode portion associated with a control gate of a memory cell, the first decode portion supports a plurality of modes based on the address and control signals, the modes comprising;

an erase mode, wherein the first decode portion couples the erase voltage terminal to the first voltage output when the memory cell is selected and the control signals indicate an erase mode;

a program select mode, wherein the first decode portion couples the read voltage terminal to the first voltage output when the memory cell is selected and the control signals indicate an erase mode;

a program non-select mode, wherein the first decode portion couples the program select voltage terminal to the first voltage output when the memory cell is not selected and the control signals indicate an erase mode;

a read mode, wherein the first decode portion couples the read voltage terminal to the first voltage terminal when the control signal indicate a read;

second decode portion for receiving an address and control signals, and coupled to the program select voltage terminal, and having an second voltage output, the second decode portion associated with the control gate of the memory cell, wherein the second decode portion provides the program select voltage to the second voltage output when the memory cell is selected and the control signals indicate a program mode;

p1 a transistor of a predetermined type having a control electrode coupled to a first voltage reference, a first current electrode coupled to the first voltage output, a second current electrode coupled the second voltage output and providing the control gate voltage terminal, and a bulk electrode coupled to the second current electrode.

17. A control gate driver circuit for selectively driving a control gate of an erasable programmable nonvolatile memory cell, comprising:

a level shifter having a first power supply input terminal, a second power supply input terminal coupled to a first power supply voltage terminal, an enable input terminal for receiving a control signal, and an output terminal coupled to the control gate, wherein said level shifter provides a voltage of said first power supply input terminal to said output terminal thereof if said control signal is active;

a first reference voltage source having an output which provides a first reference voltage which biases the control gate in a read mode of operation;

a second reference voltage source having an output which provides a second reference voltage which biases the control gate in an erase mode of operation;

a third reference voltage source having an output which provides a third reference voltage which biases the control gate in a program mode of operation; and

a selection circuit having a first input terminal coupled to said output terminal of said first reference voltage source, a second input terminal coupled to said output terminal of said second reference voltage source, a third input terminal coupled to said output terminal of said third reference voltage source, and an output terminal coupled to said first power supply input terminal of said level shifter.

18. The control gate driver circuit of claim 17 wherein said output terminal of said level shifter is coupled to the control gate through a transistor having a first current electrode coupled to said output terminal of said level shifter, a control electrode for receiving a fourth reference voltage, and a second current electrode coupled to the control gate.

19. The control gate driver circuit of claim 18 wherein said transistor is a P-channel metal-oxide-semiconductor (MOS) transistor.

20. The control gate driver circuit of claim 18 wherein said transistor further has a bulk electrode coupled to said first current electrode thereof.

21. The control gate driver circuit of claim 17 wherein said level shifter further has a second enable input terminal for receiving a decoded signal, and wherein said level shifter further provides said voltage of said first power supply input terminal to said out-put terminal thereof if said decoded signal is active while said control signal is inactive.

22. The control gate driver circuit of claim 21 wherein said control signal is active in said read mode, and wherein said decoded signal is selectively active in said erase mode and said program mode in dependence on whether an input address selects the erasable programmable nonvolatile memory cell.

23. A memory comprising:

an array of erasable programmable memory cells located at intersections of a plurality of rows and a plurality of columns, wherein each erasable programmable nonvolatile memory cell has a control gate and a select gate coupled to one of said plurality of rows, said array having a top and a bottom;

a first decoder below said bottom of said array and responsive to a row address for providing a plurality of first row select signals to said select gate of each erasable programmable nonvolatile memory cell in said array, wherein each first row select signal is coupled to said select gate of each erasable programmable nonvolatile memory cell along a corresponding row; and

a second decoder above said top of said array and responsive to said row address for providing a plurality of second row select signals to said control gate of each erasable programmable nonvolatile memory cell in said array, wherein each second row select signal is coupled to said control gate of each erasable programmable nonvolatile memory cell along a corresponding row.

24. The memory of claim 23 wherein said second decoder is characterized as being a high voltage decoder.

25. The memory of claim 23 wherein:

said first decoder has an input terminal for receiving said row address, a first output terminal for providing said plurality of first row select signals, and a second output terminal for providing a plurality of predecoded signals;

said second decoder has an input terminal for receiving said plurality of predecoded signals, and an output terminal for providing said plurality of second row select signals; and

said plurality of predecoded signals travel between said first decoder and said second decoder through said array.