Circuitry for controlling a threshold voltage in a flash memory cell

• US 5,721,705 A
• Filed: 12/19/1996
• Issued: 02/24/1998
• Est. Priority Date: 12/20/1995
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Sone, Jae Hyun, Hong, Soon Won
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/769,507
• Time in Patent Office: 432 Days
• Field of Search: 365/185.2, 365/185.24, 365/185.33
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming

Abstract

The circuit for controlling the threshold voltage in the flash memory cell according to the present invention comprises a circuit for generating a first voltage depending on the amount of a drain current in the memory cell; a first element for comparing the first voltage with a reference voltage and for generating a second voltage; and a second element for supplying a control gate voltage for the control gate of the memory cell depending on the second voltage.

Claims

1. A circuitry for controlling a threshold voltage in a flash memory cell comprising:

a circuit generating a first voltage depending on the mount of a drain current in said memory cell;

a first element generating a second voltage by comparing the first voltage of said circuit with a reference voltage; and

a second element supplying a control gate voltage to a control gate of said memory cell depending on the second voltage of said first element.

2. The circuitry claimed in claim 1 wherein said circuit comprises an operational amplifier of which a non-inverse terminal is supplied with a power supply, an inverse terminal is connected to the memory cell and the output terminal is connected to said first element and a reference resister connected between said output terminal of said operational amplifier and said inverse terminal of said operational amplifier.

3. The circuitry claimed in claim 2, wherein said reference resister is set so that the first voltage is higher than the reference voltage when said memory cell is erased to a lower threshold voltage than a desired threshold voltage.