Method and apparatus for dynamic conversion of computer instructions

• US 5,721,854 A
• Filed: 08/27/1996
• Issued: 02/24/1998
• Est. Priority Date: 11/02/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ebcioglu, Mahmut Kemal, Groves, Randall Dean
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): VU, VIET DUY
• Application Number:
  US08/703,804
• Time in Patent Office: 546 Days
• Field of Search: 395/379, 395/382, 395/384, 395/389, 395/390, 395/583, 395/733, 395/391, 395/392, 395/706
• US Class Current: 712/203
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.

Claims

1. A method of executing a computer program, compiled for sequential instruction execution, on a parallel instruction processing system, the method comprising the steps of:

retrieving, in response to a cache miss, a group of sequential instructions having a first and second conditional branch instruction, and first and second instructions that are dependent upon the first and second conditional branch instructions, respectively;

creating a compound instruction for parallel execution including the steps of;

inserting, for each of the first and second conditional branch instructions, a branch operation, and a branch address, into the compound instruction, the branch condition indicating the condition to be tested, and the branch address indicating where to proceed if the branch is executed;

inserting, for each of the first and second dependent instructions, a target register, a source operand, an operation indicator, and a dependency indicator, the operation indicator indicating the type of operation to be performed, the source operand indicating the register containing the data for the operation, the target register for containing the result of the operation, and the dependency indicator for indicating whether the execution of the instruction depends upon either the first or second conditional branch instruction; and

storing the address of the next sequential instruction;

storing the compound instruction in the cache; and

indexing the cache according to the address of the first sequential instruction in the compound instruction;

detecting an exception from the execution of one of the instructions in the compound instruction; and

executing, in response to the exception, the instructions stored in the compound instruction sequentially.

2. An apparatus for executing a computer program, compiled for sequential instruction execution, on a parallel instruction processing system, the apparatus comprising:

means for retrieving, in response to a cache miss, a group of sequential instructions having a first and second conditional branch instruction, and first and second instructions that are dependent upon the first and second conditional branch instructions, respectively;

means for creating a compound instruction for parallel execution including;

means for inserting, for each of the first and second conditional branch instructions, a branch operation, and a branch address, into the compound instruction, the branch condition indicating the condition to be tested, and the branch address indicating where to proceed if the branch is executed;

means for inserting, for each of the first and second dependent instructions, a target register, a source operand, an operation indicator, and a dependency indicator, the operation indicator indicating the type of operation to be performed, the source operand indicating the register containing the data for the operation, the target register for containing the result of the operation, and the dependency indicator for indicating whether the execution of the instruction depends upon either the first or second conditional branch instruction; and

means for storing the address of the next sequential instruction;

means for storing the compound instruction in the cache;

means for indexing the cache according to the address of the first sequential instruction in the compound instruction;

means for detecting an exception from the execution of one of the instructions in the compound instruction; and

means for executing, in response to the exception, the instructions stored in the compound instruction sequentially.