Counter control circuit in a burst memory

• US 5,721,859 A
• Filed: 11/07/1995
• Issued: 02/24/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A.
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US08/553,156
• Time in Patent Office: 840 Days
• Field of Search: 395/421.07, 395/421.08, 395/421.09, 395/421.1, 365/233, 365/222, 365/233.5, 365/189.05, 365/230.08, 365/421.07, 365/421.08, 365/401
• US Class Current: 365/236
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The column address is changes in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer.

Claims

1. A memory device having a plurality of addressable memory elements comprising:

an address counter to receive a first memory element address and adapted to generate a series of memory element addresses in response to a first transition direction of an address latch signal; and

a buffer circuit to latch the series of memory element addresses in response to a second transition direction of the address latch signal;

the buffer circuit comprises;

a first multiplexer circuit having a first input coupled to an output of the address counter;

a feed back circuit coupled between an output of the first multiplexer circuit and a second input of the first multiplexer circuit; and

a latch circuit interposed between the output of the first multiplexer circuit and the feedback circuit, and adapted to receive an output of the first multiplexer circuit.

2. The memory device of claim 1 wherein the address latch signal is an active low column address signal (CAS*).

3. The memory device of claim 2 wherein the first transition direction of the address latch signal is a low to high transition in the CAS*.

4. The memory device of claim 2 wherein the second transition direction of the address latch signal is a high to low transition in the CAS*.

5. The memory device of claim 1 wherein the series of memory element addresses is one of a plurality of predetermined burst address sequences.

6. The memory device of claim 5 where the plurality of predetermined burst address sequences comprises an interleaved address sequence and a linear address sequence.

7. The memory device of claim 1 further comprising an address sequence select circuit electrically coupled to the address counter.

8. The memory device of claim 1 wherein the buffer circuit comprises:

a multiplexer circuit responsive to the address latch signal for receiving and latching the series of memory element addresses.

9. The memory device of claim 8 wherein the buffer circuit further comprises:

a second multiplexer circuit to latch the first memory element address.

10. An integrated memory circuit comprising:

a memory array having a plurality of addressable memory cells;

an address counter to receive a first memory cell address and adapted to generate a series of memory cell addresses in response to a first transition direction of an address latch signal;

a buffer circuit coupled to the address counter to latch either the first memory cell address or the series of memory cell addresses in response to a second transition direction of the address latch signal; and

access circuitry to access the memory array in response to an address latched in the buffer circuit;

the buffer circuit comprises;

a first multiplexer circuit having a first input coupled to an output of the address counter;

a feed back circuit coupled between an output of the first multiplexer circuit and a second input of the first multiplexer circuit; and

a latch circuit interposed between the output of the first multiplexer circuit and the feedback circuit, and adapted to receive an output of the first multiplexer circuit.

11. The integrated memory circuit of claim 10 wherein the address latch signal is an active low column address signal (CAS*).

12. The integrated memory circuit of claim 11 wherein the first transition direction of the address latch signal is a low to high transition in the CAS*.

13. The integrated memory circuit of claim 11 wherein the second transition direction of the address latch signal is a high to low transition in the CAS*.

14. The integrated memory circuit of claim 10 wherein the buffer circuit further comprises:

a second multiplexer circuit having a first input coupled to an external address input and a second input coupled to the output of the first multiplexer circuit.

15. The integrated memory circuit of claim 10 wherein the address counter comprises:

a plurality of flip-flops;

a shift register coupled to the plurality of flip-flops; and

a multiplexer for enabling one of a plurality of counting sequences.

16. A method of accessing memory elements in a memory device, the method comprising the steps of:

receiving a first memory element address on address inputs;

latching the first memory element address in an address counter;

generating a series of memory element addresses with the address counter in response to a first transition direction of an address latch signal; and

latching the series of memory element addresses with a buffer circuit in response to a second transition direction of the address latch signal, the step of latching the series of memory element addresses comprises the sub-steps of;

coupling the first memory element address to a latch in the buffer circuit via a multiplex circuit,

coupling an output of the latch through a feedback circuit and the multiplex circuit to an input of the latch on the first transition direction of the address latch signal, and

coupling a subsequent memory element address from the address counter to the input of the latch on the second transition direction of the address latch signal.

17. The method of claim 16 further including the step of:

accessing a memory element based upon the series of memory element addresses latched in the buffer circuit in response to the second transition direction of the address latch signal.

18. The method of claim 17 wherein the series of memory element addresses is generated in a selectable one of a plurality of predetermined sequences.

19. The method of claim 16 further including the step of:

latching the first memory element address in the buffer circuit simultaneously with the step of latching the first memory element address in the address counter.

20. A method of accessing memory elements in a memory device, the method comprising the steps of:

receiving a first memory element address on address inputs;

latching the first memory element address in an address counter and a buffer circuit on a first active transition of an address latch signal;

generating a series of memory element addresses with the address counter in response to subsequent in-active transitions of the address latch signal; and

latching the series of memory element addresses in the buffer circuit in response to active transitions of the address latch signal, the step of latching the series of memory element addresses comprises the sub-steps of;

coupling the first memory element address to a latch in the buffer circuit via a multiplex circuit,

coupling an output of the latch through a feedback circuit and the multiplex circuit to an input of the latch on the active transition of the address latch signal, and

coupling a subsequent memory element address from the address counter to the input of the latch on the inactive transition of the address latch signal.

21. The method of claim 20 further including the step of:

accessing a memory element based upon the series of memory element addresses latched in the buffer circuit in response to the second transition direction of the address latch signal.

22. The method of claim 20 wherein the series of memory element addresses is generated in a selectable one of a plurality of predetermined sequences.