System and method for implementing parallel image processing

• US 5,721,883 A
• Filed: 01/23/1996
• Issued: 02/24/1998
• Est. Priority Date: 03/28/1994
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Katsuo, Satoshi, Shigata, Taro
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/535,218
• Time in Patent Office: 763 Days
• Field of Search: 395/706, 395/800, 395/505, 395/501, 395/524
• US Class Current: 345/505
• CPC Class Codes: G06F 8/456 Parallelism detection
• CPC Class Codes: G06T 1/00 General purpose image data processing

Abstract

A system for performing parallel processing of images. The image data to be processed is supplied to multiple arithmetic processors by a data supply control unit. Each of the processors operates on a portion of the data to produce a multiple of partial image processing results, and the partial results are integrated to form a final result. Thereby, allowing image processing to be conducted at an increased speed.

Claims

1. An image processing method for implementation on a computer having a plurality of arithmetic processors and being controllable through a computer program, the method comprising:

analyzing a control statement of said computer program to determine whether or not a parallel image processing identifier has been attached to said control statement;

when said parallel image processing identifier has been attached to said control statement;

generating a plurality of execution codes for use by said arithmetic processors to carry out parallel processing of at least one image; and

processing said images through said arithmetic processors according to said execution codes;

wherein said step of analyzing includes a step of determining whether or not the number of images subjected to image processing can be divided by the number of arithmetic processors without a remainder, and

wherein when the number of images subjected to image processing can be divided by the number of arithmetic processors without a remainder, the step of generating execution codes is performed such that said images are divided equally among said arithmetic processors for processing.

2. An image processing method for implementation on a computer having a plurality of arithmetic processors and being controllable through a computer program the method comprising:

analyzing a control statement of said computer program to determine whether or not a parallel image processing identifier has been attached to said control statement;

when said parallel image processing identifier has been attached to said control statement;

generating a plurality of execution codes for use by said arithmetic processors to carry out parallel processing of at least one image; and

processing said images through said arithmetic processors according to said execution codes; and

wherein said images are partitioned into a plurality of small areas for processing and said step of analyzing includes a step of determining whether or not the number of small areas subjected to image processing can be divided by the number of arithmetic processors without a remainder, and

wherein when the number of small areas cannot be divided by the number of arithmetic processors without a remainder, the step of generating execution codes includes generating an execution code or codes that inhibits writing the processing result until said remainder has been processed.

3. An image processing apparatus comprising:

a plurality of arithmetic processors for performing parallel processing on at least one image;

control means for selecting between a first processing mode and a second processing mode;

wherein in said first processing mode one or more of said images is partitioned into a plurality of small areas, said small areas are divided among said arithmetic processors for processing, and the processed small areas are combined to form one or more processed images; and

in said second processing mode each said arithmetic processor processes one or more entire images; and

data supply control means for integrating the processed data output by said arithmetic processors.

4. An image processing apparatus as set forth in claim 3, wherein when the number of images to be processed is 1 or a value obtained by dividing the number of images by the number of arithmetic processors has a remainder, said control means selects the first processing mode, and when the number of images can be divided by the number of arithmetic processors without a remainder, said control means selects the second processing mode.

5. An image processing method for implementation on a computer having a plurality of arithmetic processors and being controllable through a computer program, the method comprising:

analyzing a control statement of said computer program to determine whether or not a parallel image processing identifier has been attached to said control statement; and

when said parallel image processing identifier has been attached to said control statement, generating a plurality of execution codes for use by said arithmetic processors to carry out parallel processing at least one image;

wherein said step of analyzing includes a step of determining whether or not the number of images subjected to image processing can be divided by the number of arithmetic processors without a remainder, and

wherein when the number of images subjected to image processing can be divided by the number of arithmetic processors without a remainder, the step of generating execution codes is performed such that said images are divided equally among said arithmetic processors for processing.

6. An image processing method for implementation on a computer having a plurality of arithmetic processors and being controllable through a computer program, the method comprising:

analyzing a control statement of said computer program to determine whether or not a parallel image processing identifier has been attached to said control statement; and

when said parallel image processing identifier has been attached to said control statement, generating a plurality of execution codes for use by said arithmetic processors to carry out parallel processing at least one image;

wherein said images are partitioned into a plurality of small areas for processing and said step of analyzing includes a step of determining whether or not the number of small areas subjected to image processing can be divided by the number of arithmetic processors without a remainder, and

wherein when the number of small areas cannot be divided by the number of arithmetic processors without a remainder, the step of generating execution codes includes generating an execution code or codes that inhibits writing the processing result until said remainder has been processed.