Synchronizer circuit which controls switching of clocks based upon synchronicity, asynchronicity, or change in frequency

• US 5,721,886 A
• Filed: 11/30/1995
• Issued: 02/24/1998
• Est. Priority Date: 11/30/1995
• Status: Expired due to Fees

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Miller, Robert J.
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US08/565,519
• Time in Patent Office: 817 Days
• Field of Search: 395/551, 395/559, 395/306, 395/308, 395/309, 395/311
• US Class Current: 713/400
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

A synchronizer circuit which bypasses synchronous clock signals or maintains synchronicity of synchronous clock signals without degrading system performance. The synchronizer circuit includes a synchronizer having first and second clock signal inputs. A switching circuit couples to the first clock signal and to the output of the synchronizer. The synchronizer circuit is preferably programmable, and includes a control circuit which determines whether the first and second frequencies are synchronous or asynchronous, which causes the switching circuit to select the synchronizer output when the first and second frequencies are asynchronous, and which causes the switching circuit to select the first clock signal when the first and second frequencies are synchronous. The switching circuit may also couple to a first stage output of the synchronizer, and the control circuit may cause the switching circuit to select the first stage output when the first and second frequencies are synchronous and either of the first and second frequencies is a multiple of the other. The switching circuit may also include logic elements for decoupling the first and second clock signals from a multi-frequency device when the first and second frequencies are changing.

Claims

1. A circuit for synchronizing first and second frequencies of first and second clock signals comprising:

a synchronizer including

a first flip-flop circuit coupled to the first and second clock signals and having an output; and

a second flip-flop circuit having a first input coupled to the output of the first flip-flop, a second input coupled to the second clock signal, and an output;

a switching circuit having first and second inputs and an output, wherein the first input is coupled to the first clock signal and the second input is coupled to the output of the second flip-flop circuit; and

control circuit which determines whether the first and second frequencies are synchronous or asynchronous, which causes the switching circuit to select the first input of the switching circuit when the first and second frequencies are asynchronous, and which causes the switching circuit to select the second input of the switching circuit when the first and second frequencies are synchronous.

2. The circuit as recited in claim 1, wherein the control circuit comprises:

a frequency monitor coupled to the first and second clock signals which determines whether the first and second frequencies are synchronous or asynchronous; and

a controller coupled to the frequency monitor which controls the switching circuit.

3. The circuit as recited in claim 2, wherein the control circuit further comprises:

firmware containing program instructions used by the controller in controlling the switching circuit.

4. The circuit as recited in claim 1, wherein the control circuit also determines whether at least one of the first and second frequencies is changing.

5. The circuit as recited in claim 4, wherein the switching circuit further comprises:

a third input coupled to the second clock signal; and

a second output representing the second clock signal;

wherein the switching circuit decouples the first and second clock signals and the output of the synchronizer from a multi-frequency device when at least one of the first and second frequencies is changing.

6. The circuit as recited in claim 5, wherein the switching circuit comprises:

a multiplexor having an output;

a first AND gate coupled to the output of the multiplexor and to the control circuit for decoupling the first clock signal from the multi-frequency device in the absence of an enable signal from the control circuit; and

a second AND gate coupled to the second clock signal and to the control circuit for decoupling the second clock signal from the multi-frequency in the absence of the enable signal from the control circuit.

7. The circuit as recited in claim 1, wherein the switching circuit comprises a multiplexor.

8. A circuit for synchronizing first and second frequencies of first and second clock signals comprising:

a two-stage synchronizer including a first stage having first and second inputs coupled to the first and second clock signals and an output, and having a second stage having a first input coupled to the output of the first stage and a second input coupled to the second clock signal and an output;

a switching circuit having first, second, and third inputs and an output, wherein the first input is coupled to the first clock signal and the second input is coupled to the output of the second stage and the third input is coupled to the output of the first stage; and

control circuit which determines whether the first and second frequencies are synchronous or asynchronous, and which causes the switching circuit to select the second input of the switching circuit when the first and second frequencies are asynchronous, the third input of the switching circuit when the first and second frequencies are synchronous and either of the first and second frequencies is an integer multiple of the other, and the first input of the switching circuit when the first and second frequencies are synchronous and either of the first and second frequencies is not an integer multiple of the other.

9. The circuit as recited in claim 8, wherein the first stage comprises:

a first flip-flop circuit.

10. The circuit as recited in claim 9, wherein the second stage comprises:

a second flip-flop circuit.

11. The circuit as recited in claim 8, wherein the control circuit comprises:

a frequency monitor coupled to the first and second clock signals which determines whether the first and second frequencies are synchronous or asynchronous; and

a controller coupled to the frequency monitor which controls the switching circuit.

12. The circuit as recited in claim 11, wherein the control circuit further comprises:

firmware containing program instructions used by the controller in controlling the switching circuit.

13. The circuit as recited in claim 8, wherein the frequency monitor also determines whether at least one of the first and second frequencies is changing.

14. The circuit as recited in claim 13, wherein the switching circuit further comprises:

a fourth input coupled to the second clock signal; and

a second output representing the second clock signal;

wherein the switching circuit decouples the first and second clock signals and the first and second outputs of the first and second stages of the synchronizer from a multi-frequency device when at least one of the first and second frequencies is changing.

15. The circuit as recited in claim 14, wherein the switching circuit comprises:

a multiplexor having an output;

a first AND gate coupled to the output of the multiplexor and to the control circuit for decoupling the first clock signal from the multi-frequency device in the absence of an enable signal from the control circuit; and

a second AND gate coupled to the second clock signal and to the control circuit for decoupling the second clock signal from the multi-frequency in the absence of the enable signal from the control circuit.

16. The circuit as recited in claim 8, wherein the switching circuit comprises a multiplexor.