Dishing and erosion monitor structure for damascene metal processing

• US 5,723,874 A
• Filed: 06/24/1996
• Issued: 03/03/1998
• Est. Priority Date: 06/24/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leidy, Robert Kenneth, Nadeau, Rock, Brooks, Daniel Shaw, McGuire, Anne Elizabeth, Baker, Faye Diann
• Primary Examiner(s): Meier, Stephen
• Assistant Examiner(s): Wilson, Allan R.
• Application Number:
  US08/668,895
• Time in Patent Office: 617 Days
• Field of Search: 257/48, 257/621, 324/671, 324/688, 371/22.5, 437/8, 437/974
• US Class Current: 257/48
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to the preferred embodiment, an erosion and dishing monitor is provided that facilitates the accurate optimization of a planarization process as in semiconductor process. The dishing monitor comprises at least two monitor structure sets embedded in a semiconductor substrate, the monitor structure sets comprising a plurality of monitor structures connected together with a plurality of connective conductors. The erosion monitor comprises a plurality of elongated conductors embedded into a semiconductor substrate, the plurality of conductors having varying conductor widths and adjacent substrate widths.

Claims

1. A monitor for characterizing the dishing occurring in a planarization process comprising:

a) a wafer;

b) a first monitor structure set embedded in said wafer, said first monitor structure set comprising a first plurality of monitor structures, said first plurality of monitor structures connected together in series with a first plurality of connective traces; and

c) a second monitor structure set embedded in said wafer, said second monitor structure set comprising a second plurality of monitor structures, said second plurality of monitor structures having an area less than said first plurality of monitor structures and connected together in series with a second plurality of connective traces.

2. The monitor of claim 1 wherein said first plurality of monitor structures comprise substantially identical structures.

3. The monitor of claim 1 wherein said first plurality of monitor structures comprise substantially identical rectangular metal regions having a predetermined length to width ratio.

4. The monitor of claim 3 wherein said predetermined length to width ratio is in the range of 0.20:

1 to 5;

1.

5. The monitor of claim 1 wherein said first and second plurality of connective channels comprise a plurality of damascene connectors between each of said first and second plurality of monitor structures.

6. The monitor of claim 1 wherein said first and second plurality of monitor structures each comprise damascene deposited rectangular metal regions having equal predetermined length to width ratios.

7. The monitor of claim 1 wherein said first and second plurality of monitor structures comprise an equal number of monitor structures having the same number of conductivity squares.

8. The monitor of claim 1 wherein said first and second monitor structure set each include a current input and a voltage input such that conductivity is measurable using a four-point probe method.

9. The monitor of claim 1 wherein said first plurality of monitor structures has a predetermined ideal conductivity and wherein said second plurality of monitor structures has a predetermined ideal conductivity proportional to said predetermined conductivity for said first plurality of monitor structures.

10. A monitor for characterizing the erosion of a planarization process comprising:

a) a wafer;

b) a first erosion monitor embedded in said wafer, said first erosion monitor comprising at least one elongated conductor, said elongated conductor having a first predetermined width and a first width of adjacent portions of the wafer;

c) a second erosion monitor embedded in said wafer, said second erosion monitor comprising at least one elongated conductor, said elongated conductor having a second predetermined width and a second width of adjacent portions of the wafer.

11. The erosion monitor of claim 10 wherein said first and second elongated conductors comprise intertwined serpentine conductors.

12. The erosion monitor of claim 10 wherein said first and second elongated conductors comprise twin intertwined serpentine conductors.

13. The erosion monitor of claim 10 wherein said first and second elongated conductors have a predetermined ideal conductivity.

14. A monitor for characterizing the dishing of a planarization process comprising:

a wafer including a plurality of recessed regions in the surface of the wafer, said recessed regions comprising a first plurality of substantially identical rectangular subregions having a predetermined length to width ration of between about 0.20;

1 and 5;

1, each first subregion being connected to at least one other first subregion by a plurality of connective channels;

said recessed regions further comprising a second plurality of subregions, each second subregion having a predetermined length to width ration equal to that of the first subregions and being of a smaller area than said first subregions and each second subregion being connected to at least one other second subregion by a plurality of conductive channels.

15. The monitor of claim 14 wherein said recessed regions comprise regions etched into said wafer as part of a damascene deposition process.

16. A monitor for characterizing the erosion of a planarization process comprising:

a wafer including a plurality of recessed regions in the surface of the wafer, said recessed regions comprising a first subset of elongated recessed regions forming a first predetermined area percentage of recessed to non-recessed surface;

said recessed regions further comprising a second subset of elongated recessed regions having a different predetermined percentage of recessed to non-recessed surface.

17. The monitor of claim 16 wherein said recessed regions comprise regions etched into said wafer as part of a damascene deposition process.