Semiconductor device including a ferroelectric film and control method thereof

• US 5,723,885 A
• Filed: 03/13/1996
• Issued: 03/03/1998
• Est. Priority Date: 06/08/1995
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/614,578
• Time in Patent Office: 720 Days
• Field of Search: 257/295, 257/410, 257/411, 257/401, 365/117, 365/65, 365/145, 365/177, 365/184, 365/104
• US Class Current: 257/295
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A non-volatile semiconductor device can be obtained which is capable of enhancing integration level and performing accurate control of operations. A memory cell transistor of the semiconductor device in accordance with the present invention has a gate dielectric film including a ferroelectric film between a gate electrode and a semiconductor region. A back electrode is formed at the semiconductor region in a position corresponding to the gate electrode. A channel is formed at a channel formation region of the semiconductor region by applying a voltage to the back electrode, and the ferroelectric film is polarized as desired by the difference in potential between the channel and the gate electrode. Information can thus be written into the memory cell.

Claims

1. A semiconductor device with a memory cell, said memory cell comprising:

a first semiconductor region of a first conductivity type forming a channel region;

second semiconductor regions of a second conductivity type forming a pair of source/drain regions formed at both ends of said first semiconductor region;

a gate dielectric film formed on one main surface of said first semiconductor region and having a ferroelectric film;

a gate electrode formed on said ferroelectric film; and

a back electrode formed on another main surface of said first semiconductor region at a position corresponding to said gate electrode with an insulating film interposed therebetween.

2. The semiconductor device according to claim 1, wherein

the insulating film interposed between said back electrode and said another main surface of said first semiconductor region includes a ferroelectric film.

3. The semiconductor device according to claim 1, wherein

said gate electrode and said back electrode are each formed in a strip, and said gate electrode and said back electrode are disposed to extend in directions different from each other.

4. The semiconductor device according to claim 1, wherein

said gate electrode and said back electrode are each formed in a strip and disposed to extend in directions different from each other, and a source region and a drain region formed at one memory cell are disposed to extend in directions different from the directions in which said gate electrode and said back electrode extend.

5. The semiconductor device according to claim 1, wherein

said gate electrode and said back electrode are each formed in a strip and disposed to extend in directions different from each other, and an angle formed by the directions in which said gate electrode and said back electrode of a memory cell extend is substantially a right angle at a position where said gate electrode and said back electrode are overlapped with each other.

6. A semiconductor device comprising:

a plurality of memory cells arranged in row and column directions each including;

a first semiconductor region of a first conductivity type forming a channel region;

second semiconductor regions of a second conductivity type forming a pair of source/drain regions formed at both ends of said first semiconductor region;

a gate dielectric film formed on one main surface of said first semiconductor region and having a ferroelectric film;

a gate electrode formed on said ferroelectric film; and

a back electrode formed on another main surface of said first semiconductor region at a position corresponding to said gate electrode with an insulating film interposed therebetween.

7. A method of controlling a semiconductor device, comprising the steps of:

forming an inversion layer, at a first semiconductor region of a first conductivity type constituting a channel region which has one main surface and another main surface, by applying a prescribed voltage to a back electrode formed under said another main surface of said first semiconductor region with an insulating film interposed therebetween;

applying a prescribed voltage to second semiconductor regions of second conductivity type constituting source/drain regions formed in contact with both ends of said first semiconductor region, and setting a potential of the inversion layer equal to that of the source/drain regions; and

applying a voltage of an arbitrary value to a gate electrode formed on said one main surface of said first semiconductor region with a gate dielectric film having a ferroelectric film interposed therebetween, and polarizing the ferroelectric film in the gate dielectric film by a difference in potential between the gate electrode and the inversion layer.

8. The method of controlling a semiconductor device according to claim 7, wherein

in the step of polarizing said ferroelectric film, said ferroelectric film attain a plurality of polarization states.

9. The method of controlling a semiconductor device according to claim 7, wherein

said first semiconductor region includes p type impurity,

said source/drain regions include n type impurity,

a positive voltage is applied to said back electrode in the step of forming said inversion layer, and

either positive or negative voltage is applied to said gate electrode in the step of polarizing said ferroelectric film.

10. The method of controlling a semiconductor device according to claim 7, wherein

said first semiconductor region includes n type impurity,

said source/drain regions include a p type impurity,

a negative voltage is applied to said back electrode in the step of forming said inversion layer, and

either negative or positive voltage is applied to said gate electrode in the step of polarizing said ferroelectric film.