Top-drain trench based resurf DMOS transistor structure

• US 5,723,891 A
• Filed: 06/05/1995
• Issued: 03/03/1998
• Est. Priority Date: 05/18/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Malhi, Satwinder
• Primary Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/463,954
• Time in Patent Office: 1,002 Days
• Field of Search: 257/330, 257/332, 257/333, 257/335, 257/341
• US Class Current: 257/341
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

Claims

1. A transistor, comprising:

a trench formed in a semiconductor substrate;

a nonuniform dielectric lining formed in the trench, the nonuniform dielectric lining having a thin portion and a thick portion;

a drain drift region formed in the semiconductor substrate, the drain drift region abutting and substantially surrounding the thick portion of the nonuniform dielectric lining;

a drain region formed in a top surface of the semiconductor substrate in the drain drift region;

a source region formed in the semiconductor substrate, the source region abutting the thin portion of the nonuniform dielectric lining, wherein the region between the source region and the drain drift region along the thin portion of the nonuniform dielectric lining forms a channel region; and

a gate formed in the trench.

2. The transistor of claim 1 further comprising an isolation region formed below the source region, wherein the isolation region electrically isolates the source region from the semiconductor substrate.

3. A transistor, comprising:

a trench formed in a semiconductor substrate;

a nonuniform dielectric lining formed in the trench, the nonuniform dielectric lining having a thin portion and a thick portion;

a drain drift region formed in the semiconductor substrate, the drain drift region abutting and substantially surrounding the thick portion of the nonuniform dielectric lining;

a drain region formed in a top surface of the semiconductor substrate in the drain drift region;

a p-well region formed in the semiconductor substrate, the p-well region abutting and substantially surrounding the thin portion of the nonuniform dielectric lining;

a source region formed in the p-well region, the source region abutting the thin portion of the nonuniform dielectric lining, wherein the region within the p-well region between the source region and the drain drift region along the thin portion of the nonuniform dielectric lining forms a channel region; and

a gate, formed in the trench.

4. The transistor of claim 3 further comprising an isolation region formed below the p-well region, wherein the isolation region electrically isolates the source region from the semiconductor substrate.