Field programmable gate array (FPGA) with interconnect encoding

• US 5,723,984 A
• Filed: 06/06/1996
• Issued: 03/03/1998
• Est. Priority Date: 06/07/1996
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sharpe-Geisler, Bradley A.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/659,279
• Time in Patent Office: 635 Days
• Field of Search: 326/38, 326/39, 326/41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

A method of programing an FPGA to enable encoding of configuration logic block (CLB) outputs enabling an efficient use of FPGA routing resources. The method of the present invention utilizes the one hot approach, wherein only one CLB output is high at a time, to form a state machine using an FPGA. To provide encoding, programmable interconnect points (PIPs) may be programmed to connect CLB outputs to interconnect lines so that the interconnect lines indicate states of the CLB outputs in an encoded form. To provide such encoding, less interconnect lines than CLB outputs provide the encoded form of the CLB outputs. Thus, PIPs can connect a single interconnect line to more than one CLB output. Further, PIPs can connect a single CLB output to interconnect lines provided in separate parallel routing paths. To prevent erroneous results, CLB outputs which are not hot are tri-stated. Output decoding can be provided by an additional decoder in the FPGA connected to the interconnect lines providing the encoded form of the CLB outputs. Output decoding may alternatively be provided using a CLB.

Claims

1. A method of programming a field programmable gate array (FPGA) comprising the steps of:

programming configurable logic blocks (CLBs) so that only one of a number of outputs of the CLBs is high at a time; and

programming programmable interconnect points to connect the outputs of the CLBs to encoding interconnect lines so that the encoding interconnect lines indicate states of the outputs of each of the CLBs in an encoded form, the encoding interconnect lines being less in number than the CLB outputs.

2. The method of claim 1 wherein when an output of one of the CLBs is high, outputs of remaining ones of the CLBs are tri-stated.

3. The method of claim 1 wherein the encoding interconnect lines are connected to the inputs of a decoder.

4. The method of claim 1 further comprising the steps of:

programming programmable interconnect points to further connect the encoding interconnect lines to inputs of an additional CLB; and

programming the additional CLB to function as a decoder.

5. A method of encoding outputs of a CLB of a field programmable gate array (FPGA) comprising the steps of:

programming configurable logic blocks (CLBs) so that only one output of the CLBs is high at a time; and

programming programmable interconnect points to connect more than one of the CLB outputs to a single interconnect line.

6. A method of encoding outputs of a CLB of a field programmable gate array (FPGA) comprising the steps of:

programming configurable logic blocks (CLBs) so that only one output of the CLBs is high at a time; and

programming programmable interconnect points to connect one of the CLB outputs to interconnect lines provided in separate parallel routing paths.

7. A field programmable gate array (FPGA) comprising:

configurable logic blocks (CLBs) having outputs;

encoding interconnect lines; and

programmable interconnect points which are controlled to be programmed to connect the outputs of the CLBs to the encoding interconnect lines so that the encoding interconnect lines indicate states of the outputs of each of the CLBs in an encoded form, wherein the encoding interconnect lines are fewer in number than the CLB outputs.

8. The FPGA of claim 7 wherein the CLBs are controlled to be programmed so that only one of the CLB outputs is high at a time.

9. The FPGA of claim 7 further comprising:

a decoder having inputs connected to the encoding interconnect lines.

10. The FPGA of claim 7 further comprising:

an additional CLB having inputs connectable to the encoding interconnect lines, the additional CLB being programmable to function as a decoder.

11. A field programmable gate array (FPGA) comprising:

configurable logic blocks (CLBs) having outputs;

interconnect lines; and

programmable interconnect points which are controlled to be programmed to connect more than one of the CLB outputs to one of the interconnect lines.

12. A field programmable gate array (FPGA) comprising:

a configurable logic blocks (CLBs) having outputs;

interconnect lines; and

programmable interconnect points which are controlled to be programmed to connect a one of the CLB outputs to more than one of the interconnect lines provided in separate parallel routing paths.