Logic block structure optimized for sum generation

• US 5,724,276 A
• Filed: 06/17/1996
• Issued: 03/03/1998
• Est. Priority Date: 06/17/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rose, Jonathan S., Bauer, Trevor J.
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US08/664,628
• Time in Patent Office: 624 Days
• Field of Search: 364/716, 364/768, 364/784, 364/786, 364/785, 326/38, 326/39
• US Class Current: 708/235
• CPC Class Codes: G06F 2207/4812 Multiplexers
• CPC Class Codes: G06F 7/503 using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
• CPC Class Codes: G06F 7/5057 using table look-up; using programmable logic arrays G06F7/509 takes precedence
• CPC Class Codes: G06F 7/575 Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

Abstract

The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.

Claims

1. A field programmable gate array (FPGA) logic block structure comprising:

a first multiplexer having at least two data inputs and at least one control input;

a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer;

a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer;

a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer; and

a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables.

2. An FPGA logic block structure as in claim 1 further comprising:

a carry multiplexer having at least two data inputs and at least one control input, said carry multiplexer receiving as a first data input a carry-in signal from an upstream carry multiplexer and providing a carryout signal to a location external to said logic block;

one of said lines providing a second data input to said carry multiplexer, said carry multiplexer receiving as a control input one of said true and complement output signals.

3. An FPGA logic block structure as in claim 2 wherein said location external to said logic block is a downstream multiplexer.