Semiconductor memory device with reduced chip area

• US 5,724,291 A
• Filed: 11/21/1996
• Issued: 03/03/1998
• Est. Priority Date: 11/30/1995
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Matano, Tatsuya
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/754,410
• Time in Patent Office: 467 Days
• Field of Search: 365/189.01, 365/230.01, 365/189.05, 365/207, 365/230.06
• US Class Current: 365/207
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

A semiconductor memory has memory cells arranged in a matrix to form a memory cell block. A word line is connected to each row of memory cells. The cell block has a pair of data lines, a row decoder circuit for activating one of the word lines and the pair of data lines, and a column decoder circuit for generating read and write select signals to selectively activate a desired column of memory cells and set that column to either a read or write mode. Each memory cell column has a pair of digit lines, a sense amplifier for amplifying differential data signals on the digit lines and read and write data transfer circuits for transferring differential read and write data signals to the digit lines in the read and write modes. The read data transfer circuit includes a pair of first MOS transistors connected to the data lines and activated with the read select signal, and a pair of second MOS transistors connected to the first MOS transistors in series. The gates of the second MOS transistors are connected to the digit lines. The second MOS transistors are operable to drive the data lines via the first MOS transistors by the differential read data signals in the read mode. The write data transfer circuit includes a pair of third MOS transistors provided between the data lines and the digit lines and activated with the write select signal.

Claims

1. A semiconductor memory device comprising:

a memory cell block composed of a plurality of memory cells arranged in a matrix;

a pair of data lines provided for said memory cell block;

a plurality of word lines each of which is connected to a row of memory cells of said memory cell block;

a row decoder circuit provided for said memory cell block, and selectively activated in accordance with an address to activate one of said plurality of word lines and said pair of data lines;

a pair of digit lines provided for each column of memory cells of said memory cell block;

a sense amplifier provided for each column of memory cells, for amplifying differential data signals on said digit lines;

a column decoder circuit provided for said memory cell block, for selectively activating one of a plurality of columns of memory cells in accordance with said address and selectively setting the activated column of memory cells to one of a read mode and a write mode in a read/write control signal;

a read data transfer circuit provided for each column of memory cells, for respectively transferring differential read data signals to said digit lines in said read mode when the column of memory cells is activated, said differential read data signals corresponding to data read out from one memory cell of said activated column of memory cells connected to the activated word line and amplified by said sense amplifier; and

a write data transfer circuit provided for each column of memory cells, for respectively transferring differential write data signals on said data lines to said digit lines in said write mode when the column of memory cells is activated, data corresponding to said differential write data signals being written in one memory cell of said activated column of memory cells connected to the activated word line.

2. A semiconductor memory device according to claim 1, wherein said column decoder circuit generates one of a read select signal and a write select signal in accordance with said address and said read/write control signal such that said read select signal is supplied to said read data transfer circuit for said activated column of memory cells and said write select signal is supplied to said write data transfer circuit for said activated column of memory cells.

3. A semiconductor memory device according to claim 2, wherein said read data transfer circuit includes:

a pair of first MOS transistors respectively connected to said data lines and turned on in response to said read select signal; and

a pair of second MOS transistors respectively connected to said first MOS transistors in series, gates of said second MOS transistors being respectively connected to said digit lines, wherein said second MOS transistors are operable to drive said data lines via said first MOS transistors in response to said differential read data signals in said read mode.

4. A semiconductor memory device according to claim 3, wherein one electrode of each of said second MOS transistors is fixedly connected to ground potential.

5. A semiconductor memory device according to claim 3, wherein said row decoder circuit includes a potential control circuit for controlling a potential of a read drive line connected to one electrode of each of said second MOS transistors for each column of memory cells.

6. A semiconductor memory device according to claim 5, wherein said potential control circuit dynamically drives said read drive line such that the potential of said read drive line is set to a ground potential in said read mode when said memory cell block is activated and is set to a predetermined potential otherwise.

7. A semiconductor memory device according to claim 2, wherein said write data transfer circuit includes a pair of third MOS transistors respectively provided between said data lines and said digit lines and operable to be turned on in response to said write select signal.

8. A semiconductor memory device according to claim 7, wherein said row decoder circuit includes a data line precharging circuit for precharging said data lines to a potential equal to a precharge potential of said digit lines.

9. A semiconductor memory device according to claim 7, wherein said write data transfer circuit further includes a pair of fourth MOS transistors respectively provided between said data lines and said digit lines and turned on in response to a write control signal, and

wherein said row decoder circuit includes a data line precharging circuit for precharging said data lines to a potential corresponding to a higher side of said differential read data signals in said read mode when said memory cell block is activated.

10. A semiconductor memory device according to claim 9, wherein said data line precharging circuit sets potential of said data lines to a ground potential in a mode other than said read mode or when said memory cell block is not activated.

11. A semiconductor memory device comprising:

a memory cell block composed of a plurality of memory cells arranged in a matrix;

two pairs of data lines provided for said memory cell block and respectively corresponding to every two columns of memory cells;

a plurality of word lines each of which is connected to a row of memory cells of said memory cell block;

a row decoder circuit provided for said memory cell block, and selectively activated in accordance with an address to activate one of said plurality of word lines and said two pair of data lines;

a pair of digit lines provided for each column of memory cells of said memory cell block;

a sense amplifier provided for each column of memory cells, for amplifying differential data signals on said digit lines;

a column decoder circuit provided for said memory cell block, for selectively activating two of a plurality of columns of memory cells in accordance with said address and selectively setting the two activated columns of memory cells to one of a read mode and a write mode in a read/write control signal;

a read data transfer circuit provided for each column of memory cells, for respectively transferring differential read data signals on said digit lines to a corresponding one of said two pairs of digit lines in said read mode when said column of memory cells is activated by said column decoder circuit, said differential read data signals corresponding to data read out from one memory cell of said activated column of memory cells connected to the activated word line and amplified by said sense amplifiers; and

a write data transfer circuit provided for each column of memory cells, for respectively transferring differential write data signals on said data lines to the corresponding one of said two pairs of digit lines in said write mode when said column of memory cells is activated by said column decoder circuit, data corresponding to said differential write data signals being written in one memory cell of said activated columns of memory cells connected to the activated word line.

12. A semiconductor memory device according to claim 11, wherein said column decoder circuit generates one of a read select signal and a write select signal in accordance with said address and said read/write control signal such that said read select signal is supplied to said read data transfer circuits for said two activated columns of memory cells and said write select signal is supplied to said write data transfer circuits for said two activated columns of memory cells.

13. A semiconductor memory device according to claim 12, wherein said read data transfer circuit includes:

a pair of first MOS transistors respectively connected to said data lines of the corresponding pair and turned on in response to said read select signal; and

a pair of second MOS transistors respectively connected to said first MOS transistors in series, gates of said second MOS transistors being respectively connected to said digit lines, wherein said second MOS transistors are operable to drive said data lines of the corresponding pair via said first MOS transistors in response to said differential read data signals in said read mode.

14. A semiconductor memory device according to claim 13, wherein one electrode of each of said second MOS transistors is fixedly connected to ground potential.

15. A semiconductor memory device according to claim 13, wherein said row decoder circuit includes a potential control circuit for controlling a potential of a read drive line connected to one electrode of each of said second MOS transistors for each column of memory cells.

16. A semiconductor memory device according to claim 15, wherein said potential control circuit dynamically drives said read drive line such that the potential of said read drive line is set to a ground potential in said read mode when said memory cell block is activated and is set to a predetermined potential otherwise.

17. A semiconductor memory device according to claim 12, wherein said write data transfer circuit includes a pair of third MOS transistors respectively provided between said data lines of the corresponding pair and said digit lines and operable to be turned on in response to said write select signal.

18. A semiconductor memory device according to claim 17, wherein said row decoder circuit includes a data line precharging circuit for precharging said two pair of data lines to a potential equal to a precharge potential of said digit lines corresponding pairs.

19. A semiconductor memory device according to claim 17, wherein said write data transfer circuit further includes a pair of fourth MOS transistors respectively provided between said data lines of the corresponding pair and said digit lines and turned on in response to a write control signal, and

wherein said row decoder circuit includes a data line precharging circuit for precharging said two pairs of data lines to a potential corresponding to a higher side of said differential read data signals in said read mode when said memory cell block is activated.

20. A semiconductor memory device according to claim 19, wherein said data line precharging circuit sets a potential of said two pairs of data lines to a ground potential in a mode other than said read mode or when said memory cell block is not activated.

21. A semiconductor memory device comprising:

a pair of data lines on which information for a memory cell is transferred;

a sense amplifier for amplifying said information;

a pair of first transistors receiving said information amplified by said sense amplifier at control terminals;

a pair of second transistors provided between signal terminals of said pair of first transistors and said pair of data lines, for outputting said amplified information to said pair of data lines in response to a data read column select signal supplied to control terminals of said pair of second transistors; and

a pair of third transistors provided between said pair of data lines and said sense amplifier, for supplying said information on said pair of data lines to said sense amplifier in response to a data write column select signal supplied to control terminals of said pair of third transistors.