High performance n:1 multiplexer with overlap control of multi-phase clocks

• US 5,724,361 A
• Filed: 03/12/1996
• Issued: 03/03/1998
• Est. Priority Date: 03/12/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Fiedler, Alan
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Patel, Ajit
• Application Number:
  US08/614,403
• Time in Patent Office: 721 Days
• Field of Search: 370/532, 370/535, 370/537, 370/538, 370/540, 327/407
• US Class Current: 370/537
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03K 5/249 using clock signals
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

An n:1 time division multiplexer includes a multiphase clock generator, a data multiplexer, a reference multiplexer, a reference generator and a comparison circuit. The multiphase clock generator has a plurality of select clock outputs with different phases. The data multiplexer has a plurality of data inputs, a plurality of select clock inputs and a data output. The select clock inputs of the data multiplexer are coupled to corresponding select clock outputs. The reference multiplexer has a plurality of reference data inputs, a plurality of select clock inputs and a first reference output. The select clock inputs of the reference multiplexer are coupled to corresponding select clock outputs. The reference generator has a second reference output. The comparison circuit has first and second comparison inputs coupled to the first and second reference outputs, respectively, and has a comparison output coupled to the plurality of select clock outputs. The comparison output adjusts an overlap between each pair of select clock outputs that are substantially 180 degrees apart in phase as a function of a comparison between the output characteristics of the first and second reference outputs.

Claims

1. A time division multiplexer comprising:

a multiphase clock generator having a plurality of select clock outputs with different phases;

a data multiplexer having a plurality of data inputs, a plurality of select clock inputs and a data output, wherein the select clock inputs of the data multiplexer are coupled to corresponding select clock outputs;

a reference multiplexer having a plurality of reference data inputs, a plurality of select clock inputs and a first reference output, wherein the select clock inputs of the reference multiplexer are coupled to corresponding select clock outputs;

a reference generator having a second reference output; and

a comparison circuit having first and second comparison inputs coupled to the first and second reference outputs, respectively, and having a comparison output coupled to the plurality of select clock outputs.

2. The time division multiplexer of claim 1 wherein:

the reference multiplexer further includes a plurality of reference multiplexer elements which are sequentially enabled by the select clock inputs and couple the reference data inputs to the first reference output, wherein the first reference output has an output characteristic that is a function of a number of reference multiplexer elements that are enabled during transitions from one reference multiplexer element to the next; and

the second reference output has an output characteristic that is substantially the same as the output characteristic of the first reference output when a single reference multiplexer element is enabled.

3. The time division multiplexer of claim 2 wherein the reference generator comprises an additional reference multiplexer element having a continuously enabled state.

4. The time division multiplexer of claim 1 wherein the plurality of reference multiplexer elements and data multiplexer elements each comprise an open-drain NAND gate.

5. The time division multiplexer of claim 1 wherein the data multiplexer comprises an open-drain 4:

1 multiplexer having a resistive load coupled to the data output.

6. The time division multiplexer of claim 1 wherein the comparison circuit comprises a plurality of comparison outputs with each comparison output coupled to a corresponding select clock output.

7. The time division multiplexer of claim 6 wherein the comparison circuit comprises:

a first current input coupled to the first reference output;

a second current input coupled to the second reference output;

a first current source comprising a first current mirror having an input coupled to the first current input and having an output;

a first current sink comprising a second current mirror having an input coupled to the output of the first current source and having a plurality of outputs; and

a second current source comprising a third current mirror having an input coupled to the second current input and having a plurality of outputs which are coupled to corresponding outputs of the second current mirror and which form the plurality of comparison outputs.

8. The time division multiplexer of claim 1 and further comprising:

a clock buffer coupled between each select clock output and the data and reference multiplexers.

9. The time division multiplexer of claim 1 wherein the multiphase clock generator comprises:

an oscillator having at least one pair of differential clock outputs; and

a differential-to-complementary buffer having a pair of differential inputs coupled to the pair of differential clock outputs and having first and second complementary logic outputs which form the plurality of select clock outputs.

10. The time division multiplexer of claim 9 wherein the oscillator comprises a differential, voltage controlled oscillator.

11. The time division multiplexer of claim 10 wherein the differential, voltage controlled oscillator comprises:

first and second voltage controlled delay elements, each having a relatively positive and a relatively negative differential input terminal and a relatively positive and a relatively negative differential output terminal;

wherein the relatively positive and relatively negative differential output terminals of the first voltage controlled delay element for a first pair of the differential clock outputs and are coupled to the relatively positive and relatively negative differential input terminals, respectively, of the second voltage controlled delay element; and

wherein the relatively positive and relatively negative differential output terminals of the second voltage controlled delay element form a second pair of the differential clock outputs and are coupled to the relatively negative and relatively positive differential input terminals, respectively, of the first voltage controlled delay element.

12. The time division multiplexer of claim 1 wherein each delay element comprises at least two differential buffer stages.

13. The time division multiplexer of claim 1 wherein the multiphase clock generator comprises:

an oscillator comprising a plurality of differential, voltage controlled delay elements coupled together in a ring, wherein each delay element has a differential input coupled to a differential output of another delay element in the ring; and

a plurality of differential-to-complementary buffers, wherein each buffer has a differential input coupled to the differential output of a corresponding delay element and has first and second complementary logic outputs, which form the plurality of select clock outputs.

14. An n:

1 time division multiplexer comprising;

a plurality of data inputs and a data output;

a plurality of reference data inputs and a first reference output, wherein the reference data inputs are coupled to a predetermined logic level;

clock generator means for generating at least one pair of select clock signals which are approximately 180 degrees out of phase with one another and which cross over one another at a voltage between a logic HIGH level and a logic LOW level;

data multiplexer means for multiplexing the plurality of data inputs to the data output as a function of the select clock signals;

reference multiplexer means for multiplexing the plurality of reference data inputs to the first reference output as a function of the select clock signals;

reference generator means for generating a second reference output; and

p1 means coupled to the clock generator means for adjusting the voltage at which the select clock signals cross over one another as a function of the first and second reference outputs.

15. A method of serializing a plurality of parallel data inputs to a data output, comprising:

generating at least one pair of select clock signals which are approximately 180 degrees out of phase with one another and which cross over one another at a voltage between a logic HIGH level and a logic LOW level;

multiplexing the plurality of parallel data inputs to the data output as a function of the pair of select clock signals;

multiplexing a predetermined logic voltage to a first reference output as a function of the pair of select clock signals;

generating a second reference output;

comparing the first and second reference outputs; and

adjusting the voltage at which the select clock signals cross over one another as a function of the comparison.

16. The method of claim 15 wherein:

comparing the first and second reference outputs comprises comparing a current level on the first reference output with a current level on the second reference output; and

adjusting the overlap comprises;

sourcing an adjustment current into the pair of select clock signals if the current level on the first reference output is less than the current level on the second reference output; and

sinking the adjustment current out of the pair of select clock signals if the current level on the first reference output is greater than the current level on the second reference output.