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High performance n:1 multiplexer with overlap control of multi-phase clocks

  • US 5,724,361 A
  • Filed: 03/12/1996
  • Issued: 03/03/1998
  • Est. Priority Date: 03/12/1996
  • Status: Expired due to Term
First Claim
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1. A time division multiplexer comprising:

  • a multiphase clock generator having a plurality of select clock outputs with different phases;

    a data multiplexer having a plurality of data inputs, a plurality of select clock inputs and a data output, wherein the select clock inputs of the data multiplexer are coupled to corresponding select clock outputs;

    a reference multiplexer having a plurality of reference data inputs, a plurality of select clock inputs and a first reference output, wherein the select clock inputs of the reference multiplexer are coupled to corresponding select clock outputs;

    a reference generator having a second reference output; and

    a comparison circuit having first and second comparison inputs coupled to the first and second reference outputs, respectively, and having a comparison output coupled to the plurality of select clock outputs.

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