Semiconductor memory device

• US 5,724,366 A
• Filed: 10/30/1996
• Issued: 03/03/1998
• Est. Priority Date: 05/16/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Furutani, Kiyohiro
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/738,655
• Time in Patent Office: 489 Days
• Field of Search: 365/201, 365/189.07, 365/189.05, 365/225.7, 371/21.1, 371/21.2, 371/21.3
• US Class Current: 714/719
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2029/0405 comprising complete test loop
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

The drain electrode of an N type MOSFET (Q16) is connected to a power source potential (V_CC) through a fuse element (F1) (route cut-off element), and the source electrode is connected to the drain electrode of an N type MOSFET (Q17), and the drain electrode of the N type MOSFET (Q16) is connected to the input of an inverter (G16), and is also connected to a resistance element (R1) connected to a grounding potential (V_SS). Having this configuration, a semiconductor memory device incorporating a test mechanism is provided in order to test plural semiconductor memory devices by using a tester having a single data judging circuit.

Claims

1. A semiconductor device for writing and reading plural data in plural memory cells which are specified by the same address signal through a plurality of pairs of input and output wires, comprising:

a plurality of terminals,

a plurality of write means connected to said plurality of terminals respectively for writing write data in said plural of memory cells through said plurality of pairs of input and output wires,

a plurality of read means for reading data from said plural memory cells through said plurality of pairs of input and output wires,

a plurality of output means connected between said plurality of terminals and said plurality of read means respectively, for outputting a plurality of read data read out by said plurality of read means to said plurality of terminals,

a mode setting means for outputting test mode signal,

degenerating means for generating a first signal indicating that said read data connected to the said degenerating means are all at the first state, for generating a second signal indicating that said read data connected to the said degenerating means are all at the second state, for generating a third signal indicating that said read data connected to said degenerating means include read data at the first state and the second state,

comparative means connected to said degenerating means and a terminal which is one of said plurality of terminals, for comparing the output of said degenerating means with the expected data from said terminal,

test result outputting means generating a fourth signal by checking said third signal of said degenerating means and the result of comparison of said comparative means, responsive to said test mode signal of said mode setting means.

2. A semiconductor memory of device of claim 1 comprising, wherein said output means comprise buffer circuit which are set in high impedance state, at the time of input of said expected data from outside through said terminal that is connected to said buffer circuit responsive to said test mode signal of said mode setting means.

3. A semiconductor memory device of claim 1, wherein said comparative result hold means comprises:

a first hold means for holding a fifth state at the beginning of said test mode and holding a sixth state after said fourth signal of said test result outputting means indicates the incorrectness of write and read action, and at least until the end of the test mode, and

a second hold means for holding the state of said first hold means at a prescribed timing in non-volatile manner.

4. A semiconductor memory device of claim 3, wherein said second hold means has a seventh state and an eighth state, having said seventh state at the time of production and changes to said eighth state receiving said fifth state of said first holding means at said prescribed timing.

5. A semiconductor memory device of claim 4, wherein said second hold means includes a fuse element and a switch means interposed in series in a route between a signal input pin which is supplied with a first potential and a second potential, and

said switch means has a control electrode connected to the output of said test result outputting means,

said switch means becomes conductive when said first holding means hold said fifth state at said prescribed timing so that a voltage applied to said signal input pin flows a current melting said fuse element.

6. A semiconductor memory device of claim 5, wherein said first potential is higher than power source potential,

wherein said signal input pin is an address input pin,

said semiconductor memory device further comprising an address buffer connected to said address input pin, for passing an address signal inputted from said address input pin during ordinary action,

wherein said address buffer includes

a first MOS transistor of a first conductivity type having one electrode connected to said address input pin and a gate electrode connected to said address input pin,

a second MOS transistor of a second conductivity type having one electrode connected to the other electrode of said first MOS transistor and a gate electrode connected to said address input pin,

a third MOS transistor of the second conductivity type having one electrode connected to the other electrode of said second MOS transistor and the other electrode applied with said second potential, and

a fourth MOS transistor of the first conductivity type having one electrode applied with said power source potential and the other electrode connected to the other electrode of said first MOS transistor,

wherein a potential at the other electrode of said first MOS transistor is brought into said power source potential by making said third MOS transistor non-conducting and said fourth MOS transistor conducting when said fuse element is melted.