Signal processing system

• US 5,724,396 A
• Filed: 06/07/1995
• Issued: 03/03/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Claydon, Anthony Peter J., Gammack, Richard J.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US08/480,976
• Time in Patent Office: 1,000 Days
• Field of Search: 375/355, 375/360, 375/371, 375/377, 375/342, 375/326, 375/327, 364/724.1
• US Class Current: 375/355
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 2027/0028 at passband only
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 27/3872 Compensation for phase rotation in the demodulated signal
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/0335 Gardner detector
• CPC Class Codes: H04N 21/2383 Channel coding or modulation of digital bit-stream, e.g. QPSK modulation arrangements for detecting or preventing errors in the information received by adapting the channel coding H04L1/0009; analogue front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002

Abstract

A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Claims

1. A signal processing apparatus for processing signals that are sampled by a sampler operative at a sampling rate, the signals having a period corresponding to a received symbol rate, the apparatus comprising:

a clock, operative at said sampling rate;

a numerically controlled oscillator operative at periods T;

an interpolator receiving samples at said sampling rate; and

a loop filter, coupled to said interpolator and said numerically controlled oscillator and having an output responsive to a difference between said periods T and said period corresponding to said received symbol rate of said sampled signals;

wherein said numerically controlled oscillator is responsive to said output of said loop filter and generates a first output signal that is representative of an interpolation distance between succeeding samples, and said interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of interpolated samples, and said numerically controlled oscillator generates said first output signal whenever a state Ω

exceeds a division of said symbol period, and said interpolator generates said output signal representative of interpolated samples in response to said first output signal, wherein Ω

is a state representative of a number of elapsed operative periods of said numerically controlled oscillator.

2. The apparatus according to claim 1, wherein an input signal is modulated, and said interpolator is a sinc interpolator, further comprising:

an I,Q demodulator; and

a sampler, comprising first and second analog-to-digital converters respectively coupled to an in phase output and a quadrature output of said demodulator;

wherein said sinc interpolator accepts in phase and quadrature outputs of said sampler.

3. The apparatus according to claim 1, wherein said loop filter accepts an in phase component of said interpolated samples and an error signal is computed according to the equation:

##EQU11## wherein I is the in phase component;

T is the symbol period; and

r is the interval between alternate samples.

4. The apparatus according to claim 1, wherein said loop filter accepts an in phase component and a quadrature component of said interpolated samples an error signal is computed according to the equation:

##EQU12## wherein I is the in phase component;

Q is the quadrature component;

T is the symbol period; and

r is the interval between alternate samples.

5. The apparatus according to claim 1, wherein said interpolater is a sinc interpolator, said numerically controlled oscillator, said sinc interpolator, and said loop filter comprise an integrated semiconductor circuit.

6. The apparatus according to claim 5, wherein said integrated semiconductor circuit is a CMOS circuit.

7. The apparatus according to claim 1, further comprising a matched filter having an input coupled to said interpolator and an output coupled to said loop filter.

8. The apparatus according to claim 7, wherein said matched filter is a square-root raised cosine filter.

9. The apparatus according to any of claims 1-8, wherein said .first output signal of said numerically controlled oscillator further comprises a second output signal that is representative of a value Δ

according to the equation;

##EQU13## wherein;

system clock is said clock rate;

baud rate is said nominal baud rate; and

Ω

is said state representative of a number of elapsed operative periods of said numerically controlled oscillator, and said interpolator emits an interpolated sample upon receiving said second output signal.

10. The apparatus according to any of claims 1-7, further comprising an analog-to-digital converter coupled to an input of a sinc interpolator and sampling a signal at said sampling rate.

11. The apparatus according to any of claims 1-7, wherein said interpolator comprises:

a first sinc interpolator that receives an in phase component of said samples; and

a second sinc interpolator that receives a quadrature component of said samples.

12. The apparatus according to any of claims 1-7, wherein said interpolator comprises a finite impulse response filter having a bank of coefficients.

13. The apparatus according to claim 12, wherein said bank of coefficients comprises a plurality of banks, and a sinc interpolator further comprising:

an addressable memory containing a plurality of coefficients.

14. The apparatus according to any claims 1-7, wherein said interpolator is a sinc interpolator and performs a plurality of sinc interpolations that precede and follow a required sinc interpolation point, further comprising:

a linear interpolator that performs linear interpolation on said plurality of sinc interpolations.

15. The apparatus according to any of claims 1-8, wherein said periods T are initially equal to a nominal baud rate divided by said sampling rate.

16. A signal processing apparatus for processing an input signal having a period corresponding to a received symbol rate, the apparatus comprising:

a clock, operative at said sampling rate;

a numerically controlled oscillator operative at periods T;

a sinc interpolator receiving samples at said sampling rate;

wherein said interpolator comprises a finite impulse response filter operable according to a bank of coefficients, and an addressable memory having said coefficients memorized therein;

a loop filter, coupled to said sinc interpolator and said numerically controlled oscillator and having an output responsive to a difference between said periods T and said period corresponding to said received symbol rate of said sampled signals;

a sampler, comprising first and second analog-to-digital converters respectively coupled to an in phase component and a quadrature component of said signals;

wherein said sinc interpolator and said loop filter accept in phase and quadrature outputs of said sampler;

wherein said numerically controlled oscillator is responsive to said loop filter and generates an output signal that is representative of an interpolation distance between succeeding samples, and said interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of said interpolated samples; and

said numerically controlled oscillator, said sinc interpolator, and said loop filter comprise an integrated semiconductor circuit, wherein said output of said numerically controlled oscillator comprises a first output signal that is generated whenever said state Ω

exceeds a division of said symbol period, and said interpolator generates an output in response to said first output signal, wherein Ω

is a state representative of a number of elapsed operative periods of said numerically controlled oscillator.

17. The apparatus according to claim 16, wherein said integrated semiconductor circuit is a CMOS circuit.

18. The apparatus according to claim 16, further comprising a matched filter having an input coupled to said interpolator and an output coupled to said loop filter.

19. The apparatus according to claim 18, wherein said matched filter is a square-root raised cosine filter.

20. The apparatus according to claim 16, wherein said first output signal of said numerically controlled oscillator further comprises a second output signal that is representative of a value Δ

according to the equation;

##EQU14## wherein;

system clock is said clock rate;

baud rate is said nominal baud rate; and

Ω

is a state representative of a number of elapsed operative periods of said numerically controlled oscillator, and said interpolator emits an interpolated sample upon receiving said second output signal.

21. The apparatus according to any of claims 16-19, wherein said sinc interpolator comprises:

a first sinc interpolator that receives an in phase component of said samples; and

a second sinc interpolator that receives a quadrature component of said samples.

22. The apparatus according to any claims 16-19, wherein said sinc interpolator and performs a plurality of sinc interpolations that precede and follow a required sinc interpolation point, further comprising:

a linear interpolator that performs linear interpolation on said plurality of sinc interpolations.

23. The apparatus according to any claims 16-19, wherein said sampler is integrated in said integrated circuit.

24. The apparatus according to any of claims 16-19, wherein said periods T are initially equal to a nominal baud rate divided by said sampling rate.

25. A signal processing apparatus for processing signals that are sampled by a sampler operative at a sampling rate, the signals having a period corresponding to a received symbol rate, the apparatus comprising:

a clock, operative at said sampling rate;

a numerically controlled oscillator operative at periods T;

an interpolator receiving samples at said sampling rate; and

a loop filter, coupled to said interpolator and said numerically controlled oscillator and having an output responsive to a difference between said periods T and said period corresponding to said received symbol rate of said sampled signals, wherein said loop filter accepts an in phase component of said interpolated samples and an error signal is computed according to the equation;

##EQU15## wherein I is the in phase component;

T is the symbol period; and

r is the interval between alternate samples;

wherein said numerically controlled oscillator is responsive to said output of said loop filter and generated an output signal that is representative of an interpolation distance between succeeding samples, and said interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of interpolated samples.

28. The apparatus according to any of claims 25-27, wherein said interpolater is a sinc interpolator, said numerically controlled oscillator, said sinc interpolator, and said loop filter comprise an integrated semiconductor circuit.

29. The apparatus according to any of claims 25-27, further comprising a matched filter having an input coupled to said interpolator and an output coupled to said loop filter.

30. The apparatus according to any of claims 25-27, wherein said matched filter is a square-root raised cosine filter.

26. A signal processing apparatus for processing signals that are sampled by a sampler operative at a sampling rate, the signals having a period corresponding to a received symbol rate, the apparatus comprising:

a clock, operative at said sampling rate;

a numerically controlled oscillator operative at periods T;

an interpolator receiving samples at said sampling rate; and

a loop filter, coupled to said interpolator and said numerically controlled oscillator and having an output responsive to a difference between said periods T and said period corresponding to said received symbol rate of said sampled signals;

wherein said numerically controlled oscillator is responsive to said output of said loop filter and generates an output signal that is representative of an interpolation distance between succeeding samples, and said interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of interpolated samples wherein said loop filter accepts an in phase component and a quadrature component of said interpolated samples and said error signal is computed according to the equation;

##EQU16## wherein I is the in phase component;

Q is the quadrature component;

T is the symbol period; and

r is the interval between alternate samples.

27. A signal processing apparatus for processing signals that are sampled by a sampler operative at a sampling rate, the signals having a period corresponding to a received symbol rate, the apparatus comprising:

a clock, operative at said sampling rate;

a numerically controlled oscillator operative at periods T;

an interpolator receiving samples at said sampling rate, wherein said interpolator is a sinc interpolator and performs a plurality of sinc interpolations that precede and follow a required sinc interpolation point;

a linear interpolator that performs linear interpolation on said plurality of sinc interpolations;

a loop filter, coupled to said interpolator and said numerically controlled oscillator and having an output responsive to a difference between said periods T and said period corresponding to said received symbol rate of said sampled signals;

wherein said numerically controlled oscillator is responsive to said output of said loop filter and generates an output signal that is representative of an interpolation distance between succeeding samples, and said interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of said interpolated samples.

31. A signal processing apparatus for processing an input signal having a period corresponding to a received symbol rate, the apparatus comprising:

a clock, operative at said sampling rate;

a numerically controlled oscillator operative at periods T;

a sinc interpolator receiving samples at said sampling rate;

wherein said interpolator comprises a finite impulse response filter operable according to a bank of coefficients, and an addressable memory having said coefficients memorized therein, wherein said sinc interpolator and performs a plurality of sinc interpolations that precede and follow a required sinc interpolation point;

a linear interpolator that performs linear interpolation on said plurality of sinc interpolations;

a loop filter, coupled to said sinc interpolator and said numerically controlled oscillator and having an output responsive to a difference between said periods T and said period corresponding to said received symbol rate of said sampled signals;

a sampler, comprising first and second analog-to-digital converters respectively coupled to an in phase component and a quadrature component of said signals;

wherein said sinc interpolator and said loop filter accept in phase and quadrature outputs of said sampler;

wherein said numerically controlled oscillator is responsive to said loop filter and generates an output signal that is representative of an interpolation distance between succeeding samples, and said interpolator interpolates said received samples according to said interpolation distance, and produces an output signal representative of interpolated samples; and

said numerically controlled oscillator, said sinc interpolator, and said loop filter comprise an integrated semiconductor circuit.