Test mode matrix circuit for an embedded microprocessor core

• US 5,724,502 A
• Filed: 08/07/1995
• Issued: 03/03/1998
• Est. Priority Date: 08/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Colyer, Peter Stewart, Stauffer, David Robert, Cherichetti, Cory Ansel
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/511,943
• Time in Patent Office: 939 Days
• Field of Search: 395/183.04, 395/183.01, 395/183.06, 371/25.1, 371/27, 371/22.6, 364/927.81, 364/267.91, 364/550, 364/578, 324/73.1, 324/158.1, 365/201, 365/200, 307/407
• US Class Current: 714/28
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Claims

1. An integrated circuit comprising:

at least one microprocessor;

a logic circuit;

signal routing means coupled between the microprocessor and the logic circuit, for routing microprocessor operational signals directly to the logic circuit, for routing microprocessor test signals to the microprocessor, and for routing logic test signals to the logic circuit;

a plurality of I/O circuits coupled to a plurality of I/O pads;

wherein the signal routing means operates in one of a plurality of mutually-exclusive states, and wherein the signal routing means comprises a test mode matrix having a first bus coupled to the microprocessor, having a second bus coupled to the logic circuit, and having a third bus coupled to the plurality of I/O circuits, and wherein;

the test mode matrix couples the first bus to the second bus in a first of the plurality of states;

the test mode matrix couples the first bus to the third bus in a second of the plurality of states; and

the test mode matrix couples the second bus to the third bus in a third of the plurality of states.

2. The integrated circuit of claim 1 wherein the test mode matrix further comprises a fourth bus coupled to the logic circuit, and wherein the test mode matrix couples the third bus to the fourth bus in the first state.

3. An integrated circuit comprising:

a plurality of microprocessors;

a logic circuit;

signal routing means coupled between the microprocessor and the logic circuit, for routing microprocessor operational signals directly to the logic circuit, for routing microprocessor test signals to the microprocessor, and for routing logic test signals to the logic circuit;

the signal routing means comprising;

a plurality of test mode matrices, at least one test mode matrix for each of the microprocessors; and

switching means for coupling the test mode matrices corresponding to a selected one of the plurality of microprocessors to the plurality of I/O circuits;

a plurality of I/O circuits coupled to a plurality of I/O pads;

wherein the signal routing means operates in one of a plurality of mutually-exclusive states, and wherein each test mode matrix has a first bus coupled to the corresponding microprocessor, a second bus coupled to the logic circuit, and a third bus coupled to the signal routing means, and wherein;

the test mode matrix couples the first bus to the second bus in a first of the plurality of states;

the test mode matrix couples the first bus to the third bus in a second of the plurality of states; and

the test mode matrix couples the second bus to the third bus in third of the plurality of states.

4. A method for testing an integrated circuit, the integrated circuit comprising:

at least one microprocessor;

a logic circuit;

a plurality of I/O circuits coupled to a plurality of I/O pads;

switch means coupled between the microprocessor and the logic circuit,

for routing microprocessor operational signals directly to the logic circuit without passing through any of the plurality of I/O circuits;

for routing microprocessor test signals to the microprocessor; and

for routing logic test signals to the logic circuit;

wherein the switch means operates in one of a plurality of mutually-exclusive states, and wherein the switch means routes the microprocessor operational signals directly to the logic circuit when the switch means is in a first state;

means for selecting one of the plurality of states;

the method comprising the steps of;

(A) testing a microprocessor under test, comprising one microprocessor within the integrated circuit, the testing of the microprocessor under test comprising the steps of;

coupling an external tester to the plurality of I/O pads;

selecting the second state, resulting in the switch means routing the microprocessor test signals from the plurality of I/O circuits to the microprocessor under test;

the external tester applying a standard set of test vectors to the plurality of I/O pads;

the external tester monitoring signals from of the microprocessor under test on the I/O pads that result from applying the test vectors; and

the external tester indicating from the monitored signals whether the microprocessor under test is functional.

5. The method of claim 4 further comprising the step of:

(B) testing the logic circuit and code for the microprocessor, comprising the steps of;

coupling an in-circuit emulator to the plurality of I/O pads;

selecting the third state, resulting in the switch means routing the logic test signals from the plurality of I/O circuits to the logic circuit; and

the in-circuit emulator applying signals to the plurality of I/O pads to emulate the function of the microprocessor.

6. The method of claim 5 wherein the integrated circuit further comprises a plurality of microprocessors, and wherein the switch means comprises:

a plurality of test mode matrices, at least one test mode matrix for each of the microprocessors; and

second switch means for coupling the test mode matrices corresponding to a selected one of the plurality of microprocessors to the plurality of I/O circuits;

wherein the step of testing the logic circuit and code for the microprocessor further comprises the step of the second switch means coupling the corresponding test mode matrix to the plurality of I/O circuits;

wherein the step of routing the logic test signals from the plurality of I/O circuits to the logic circuit comprises the steps of;

routing the logic test signals from the plurality of I/O circuits through the second switch means; and

routing the logic test signals from the second switch means through the corresponding test mode matrix to the logic circuit.