Computer system with multiple PC card controllers and a method of controlling I/O transfers in the system
First Claim
1. A computer system comprising:
- a processor;
a first bus coupled to the processor, and a second bus coupled to the first bus by a bridge; and
at least one controller coupled to the first bus and at least one controller coupled to the second bus, each said controller coupled to the first bus having;
at least one socket in which a device is connectable, each socket being separately addressable at an input/output (I/O) address through the controller by the processor,a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies the at least one socket among all of the sockets of the plurality of controllers,an index register and at least one data register pointed to by an index stored in the index register,in which each said controller coupled to the first bus updates the index register when the processor writes to an I/O address, without acknowledging the write on the first bus, and recognizes addressing of the at least one socket of the controller by the processor, by comparing the socket pointer information with the updated index in the index register, and when at least a portion of the socket pointer information matches at least a portion of the updated index, updating with write data the data register pointed to by the index register.
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Accused Products
Abstract
A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers. The index registers of the PC card controllers are updated when the processor writes to an I/O address, without acknowledging the write on the PCI bus. This allows the writes to propagate through the system to lower levels, instead of being stopped by a subtractive decode device. To perform this, each PC card controller compares the socket pointer information with the updated index in the index register. When at least a portion of the socket pointer information matches at least a portion of the updated index, the PC card controller updates with write data the data register pointed to by the index register.
155 Citations
20 Claims
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1. A computer system comprising:
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a processor; a first bus coupled to the processor, and a second bus coupled to the first bus by a bridge; and at least one controller coupled to the first bus and at least one controller coupled to the second bus, each said controller coupled to the first bus having; at least one socket in which a device is connectable, each socket being separately addressable at an input/output (I/O) address through the controller by the processor, a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies the at least one socket among all of the sockets of the plurality of controllers, an index register and at least one data register pointed to by an index stored in the index register, in which each said controller coupled to the first bus updates the index register when the processor writes to an I/O address, without acknowledging the write on the first bus, and recognizes addressing of the at least one socket of the controller by the processor, by comparing the socket pointer information with the updated index in the index register, and when at least a portion of the socket pointer information matches at least a portion of the updated index, updating with write data the data register pointed to by the index register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A PC card controller for controlling at least one card coupled to the PC card controller, comprising:
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at least one socket for receiving the at least one card and providing controllable connectivity of the card to a system; a socket pointer register that stores socket pointer information uniquely identifying the at least one socket from any other socket in a system; a plurality of data registers that store data; and an index register that stores an index that points to one of the plurality of data registers;
in which the PC card controller is configured to write an index into the index register without acknowledging the writing of the index. - View Dependent Claims (14, 15, 16)
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17. A method of controlling input/output (I/O) transfers of data in a computer system having multiple PC card controllers that each has at least one socket into which a card is insertable, the method comprising the steps of:
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programming the PC card controllers with individually addressable socket numbers, such that each socket in the system is uniquely addressable; and writing an index into index registers of a plurality of the PC card controllers without acknowledgement of the writing of the index into the index registers, the index being addressed to a specific one of the sockets. - View Dependent Claims (18, 19, 20)
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Specification