Interface for connecting a bus to a random access memory using a two wire link
First Claim
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1. An apparatus for connecting a bus to a RAM comprising:
- a single address generator providing complete addresses that is clocked at a first clock rate;
a RAM interface, comprising;
a plurality of swing buffers connected to a bus for receiving therefrom a plurality of data words from a source at a second clock rate;
a control coupled to said swing buffers;
a two-wire link connecting said control with said address generator wherein a request/acknowledge protocol is implemented therebetween via said link, wherein said two-wire link comprises;
a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready;
wherein the interface is clocked at a third clock rate that is asynchronous with said first clock rate and said second clock rate, and data is transferred between a selected swing buffer and a RAM in response to a first signal that is generated by said control when said control receives an address from the address generator and said control receives a second signal from said selected swing buffer via said communication link.
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Abstract
The invention provides a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The interface utilizes a plurality of swing buffers, and has a control module for coordinating accesses thereto, which is connected to the address generator by a specialized two-wire interface. The address generator and the source of data are clocked asynchronously and at different clock rates.
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6 Claims
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1. An apparatus for connecting a bus to a RAM comprising:
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a single address generator providing complete addresses that is clocked at a first clock rate; a RAM interface, comprising; a plurality of swing buffers connected to a bus for receiving therefrom a plurality of data words from a source at a second clock rate; a control coupled to said swing buffers; a two-wire link connecting said control with said address generator wherein a request/acknowledge protocol is implemented therebetween via said link, wherein said two-wire link comprises;
a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready;wherein the interface is clocked at a third clock rate that is asynchronous with said first clock rate and said second clock rate, and data is transferred between a selected swing buffer and a RAM in response to a first signal that is generated by said control when said control receives an address from the address generator and said control receives a second signal from said selected swing buffer via said communication link. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification