Multiprocessor system with reduced power mode and improved variation of power demand

• US 5,724,591 A
• Filed: 01/26/1996
• Issued: 03/03/1998
• Est. Priority Date: 01/27/1995
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yoshidome, Hitoshi, Maruyama, Takashi, Hara, Tsutomu, Hattori, Ryuichi, Tobita, Tsunehiro
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/592,236
• Time in Patent Office: 767 Days
• Field of Search: 395/750, 395/800, 395/182.12, 364/707, 364/492
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessor system is provided with processor units which are grouped beforehand into some groups, a system status monitoring unit for monitoring a key input operation of a keyboard, a power demand monitoring unit for calculating the difference between the total power demand of the processor units at the present time and the total power demand of the processor units in a low power-demand mode which is measured beforehand, when the key input operation is not carried out in a normal operation mode for a predetermined time, and an operation clock controller for successively reducing or stopping operation clocks supplied to the respective processor units for each group in turn to shift the current mode to the low power-demand mode. With this construction, a power variation which occurs at the time of the switching operation between the normal operation mode and the low power-demand mode or at the time of power supply/power shut-off can be reduced.

Claims

1. A multiprocessor system having plural processor units including:

a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units is in a normal state and a second mode in which each of said plural processor units is in a low power-demand state whose consumed power is smaller than that of the normal state; and

a setting circuit for classifying said plural processor units into plural groups, each group containing at least one processor unit, to successively set said plural groups to the normal state in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the low power-demand state in turn when said reception circuit receives a setting demand requesting the second mode,

wherein said setting circuit measures the total power demand of said plural processor units when said reception circuit receives the setting demand requesting one of the first mode or the second mode, calculates the difference between the measured total power demand and a total power demand of said plural processor units in the requested mode, and collectively sets the plural processor units to the normal state or the low power-demand state in accordance with the requested mode when the calculated difference is smaller than a predetermined value.

2. The multiprocessor system as claimed in claim 1, wherein said setting circuit changes the operation frequency of said processor units to perform a setting operation of said processor units to one of the normal state and the low power-demand state.

3. The multiprocessor system as claimed in claim 2, further including an input circuit for monitoring an external operation, and a circuit for outputting the setting demand requesting the second mode to the reception circuit when the multiprocessor system is set in the first mode and the external operation monitored by said input circuit does not occur for a predetermined time and outputting the setting demand requesting the first mode to said reception circuit when the multiprocessor system is set in the second mode and the external operation monitored by said input circuit occurs.

4. The multiprocessor system as claimed in claim 2, further including a detection circuit for detecting the magnitude of the total load of respective processing steps of said plural processor units, and a circuit for outputting the setting demand requesting the second mode to said reception circuit when the first mode is set and when the magnitude of the total load detected by said detection circuit is smaller than the magnitude of a predetermined total load and this state is continued for a predetermined time, and outputting the setting demand requesting the first mode to said reception circuit when the second mode is set and when the magnitude of the total load detected by said detection circuit is larger than the magnitude of the predetermined total load.

5. The multiprocessor system as claimed in claim 1, wherein said setting circuit changes the magnitude of a voltage to be supplied to said processor units to perform the setting operation of said processor units to one of the normal state and the low power-demand state.

6. The multiprocessor system as claimed in claim 5, further including an input circuit for monitoring an external operation, and a circuit for outputting the setting demand requesting the second mode to the reception circuit when the multiprocessor system is set in the first mode and the external operation monitored by said input circuit does not occur for a predetermined time and outputting the setting demand requesting the first mode to said reception circuit when the multiprocessor system is set in the second mode and the external operation monitored by said input circuit occurs.

7. The multiprocessor system as claimed in claim 5, further including a detection circuit for detecting the magnitude of the total load of respective processing steps of said plural processor units, and a circuit for outputting the setting demand requesting the second mode to said reception circuit when the first mode is set and when the magnitude of the total load detected by said detection circuit is smaller than the magnitude of a predetermined total load and this state is continued for a predetermined time, and outputting the setting demand requesting the first mode to said reception circuit when the second mode is set and when the magnitude of the total load detected by said detection circuit is larger than the magnitude of the predetermined total load.

8. The multiprocessor system as claimed in claim 1, further including an input circuit for monitoring an external operation, and a circuit for outputting the setting demand requesting the second mode to the reception circuit when the multiprocessor system is set in the first mode and the external operation monitored by said input circuit does not occur for a predetermined time and outputting the setting demand requesting the first mode to said reception circuit when the multiprocessor system is set in the second mode and the external operation monitored by said input circuit occurs.

9. The multiprocessor system as claimed in claim 1, further including a detection circuit for detecting the magnitude of the total load of respective processing steps of said plural processor units, and a circuit for outputting the setting demand requesting the second mode to said reception circuit when the first mode is set and when the magnitude of the total load detected by said detection circuit is smaller than the magnitude of a predetermined total load and this state is continued for a predetermined time, and outputting the setting demand requesting the first mode to said reception circuit when the second mode is set and when the magnitude of the total load detected by said detection circuit is larger than the magnitude of the predetermined total load.

10. A multiprocessor system having plural processor units including:

a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units is in a normal state and a second mode in which each of said plural processor units is in a low power-demand state whose consumed power is smaller than that of the normal state; and

a setting circuit for classifying said plural processor units into plural groups, each group containing at least one processor unit, to successively set said plural groups to the normal state in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the low power-demand state in turn when said reception circuit receives a setting demand requesting the second mode,

wherein said setting circuit changes the operation frequency of said processor units to perform a setting operation of said processor units to one of the normal state and the low power-demand state.

11. The multiprocessor system as claimed in claim 10, further including an input circuit for monitoring an external operation, and a circuit for outputting the setting demand requesting the second mode to the reception circuit when the microprocessor system is set in the first mode and the external operation monitored by said input circuit does not occur for a predetermined time and outputting the setting demand requesting the first mode to said reception circuit when the multiprocessor system is set in the second mode and the external operation monitored by said input circuit occurs.

12. The multiprocessor system as claimed in claim 10, further including a detection circuit for detecting the magnitude of the total load of respective processing steps of said plural processor units, and a circuit for outputting the setting demand requesting the second mode to said reception circuit when the first mode is set and when the magnitude of the total load detected by said detection circuit is smaller than the magnitude of a predetermined total load and this state is continued for a predetermined time, and outputting the setting demand requesting the first mode to said reception circuit when the second mode is set and when the magnitude of the total load detected by said detection circuit is larger than the magnitude of the predetermined total load.

13. A multiprocessor system having plural processor units including:

a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units is in a normal state and a second mode in which each of said plural processor units is in a low power-demand state whose consumed power is smaller than that of the normal state; and

a setting circuit for classifying said plural processor units into plural groups, each group containing at least one processor unit, to successively set said plural groups to the normal state in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the low power-demand state in turn when said reception circuit receives a setting demand requesting the second mode,

wherein said setting circuit changes the magnitude of a voltage to be supplied to said processor units to perform the setting operation of said processor units to one of the normal state and the low power-demand state.

14. The multiprocessor system as claimed in claim 13, further including an input circuit for monitoring an external operation, and a circuit for outputting the setting demand requesting the second mode to the reception circuit when the multiprocessor system is set in the first mode and the external operation monitored by said input circuit does not occur for a predetermined time and outputting the setting demand requesting the first mode to said reception circuit when the multiprocessor system is set in the second mode and the external operation monitored by said input circuit occurs.

15. The multiprocessor system as claimed in claim 13, further including a detection circuit for detecting the magnitude of the total load of respective processing steps of said plural processor units, and a circuit for outputting the setting demand requesting the second mode to said reception circuit when the first mode is set and when the magnitude of the total load detected by said detection circuit is smaller than the magnitude of a predetermined total load and this state is continued for a predetermined time, and outputting the setting demand requesting the first mode to said reception circuit when the second mode is set and when the magnitude of the total load detected by said detection circuit is larger than the magnitude of the predetermined total load.

16. A multiprocessor system having plural processor units, including:

a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units is in a normal state and a second mode in which each of said plural processor units is in a low power-demand state whose consumed power is smaller than that of the normal state,

a setting circuit for classifying said plural processor units into plural groups, each group containing at least one processor unit, to successively set said plural groups to the normal state in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the low power-demand state in turn when said reception circuit receives a setting demand requesting the second mode,

an input circuit for monitoring an external operation, and

a circuit for outputting the setting demand requesting the second mode to the reception circuit when the multiprocessor system is set in the first mode and the external operation monitored by said input circuit does not occur for a predetermined time and outputting the setting demand requesting the first mode to said reception circuit when the multiprocessor system is set in the second mode and the external operation monitored by said input circuit occurs.

17. A multiprocessor system having plural processor units, including:

a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units is in a normal state and a second mode in which each of said plural processor units is in a low power-demand state whose consumed power is smaller than that of the normal state,

a setting circuit for classifying said plural processor units into plural groups, each group containing at least one processor unit, to successively set said plural groups to the normal state in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the low power-demand state in turn when said reception circuit receives a setting demand requesting the second mode,

a detection circuit for detecting the magnitude of the total load of processing steps of said plural processor units, respectively, and

a circuit for outputting the setting demand requesting the second mode to said reception circuit when the first mode is set and when the magnitude of the total load detected by said detection circuit is smaller than the magnitude of a predetermined total load and this state is continued for a predetermined time, and outputting the setting demand requesting the first mode to said reception circuit when the second mode is set and when the magnitude of the total load detected by said detection circuit is larger than the magnitude of the predetermined total load.

18. A multiprocessor system having plural processor units, including:

a reception circuit for receiving a setting demand requesting one of a first mode in which each of said plural processor units is in a normal state and a second mode in which each of said plural processor units is in a low power-demand state whose consumed power is smaller than that of the normal state, and

a setting circuit for classifying said plural processor units into plural groups, each group containing at least one processor unit, to successively set said plural groups to the normal state in turn when said reception circuit receives a setting demand requesting the first mode, and to successively set said plural processor units to the low power-demand state in turn when said reception circuit receives a setting demand requesting the second mode,

wherein said plural processor units are grouped on respective print wiring boards to be mounted.

19. A multiprocessor system having plural processors which are classified into plural groups in advance, each one of the groups containing at least one processor, said multiprocessor system including:

a generation circuit generating a setting demand requesting one of first mode in which each of said plural groups is in a normal state and a second mode in which each of said plural groups is in a low power-demand state whose consumed power is smaller than the first mode;

a reception circuit receiving said setting demand; and

a setting circuit successively setting each of said plural groups to said normal state in turn according to said setting demand requesting said first mode being received by said reception circuit, and successively setting each of said plural groups to said low power-demand state according to said setting demand requesting said second mode being received by said reception circuit.

20. The multiprocessor system as claimed in claim 19, further including an input circuit inputting a signal corresponding to an instruction received from outside said multiprocessor system and an output circuit outputting said setting demand requesting said second mode when said input circuit does not input said signal during a predetermined time while each of said plural groups are set to be in said first mode, and outputting said setting demand requesting said first mode when said input circuit inputs said signal while each of said plural groups are set to be in said second mode.