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Data processing system for accessing an external device and method therefor

  • US 5,724,604 A
  • Filed: 08/02/1995
  • Issued: 03/03/1998
  • Est. Priority Date: 08/02/1995
  • Status: Expired due to Term
First Claim
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1. A data processor, comprising:

  • a central processing unit for communicating a plurality of address values, a plurality of data values, and a plurality of control values; and

    a system integration unit, the system integration unit, comprising;

    a compare circuit coupled to the central processing unit for receiving the plurality of address values, the compare circuit providing a compare signal indicating an address range which includes a first one of the plurality of address values;

    a control circuit coupled to the central processing unit for receiving the plurality of control values and coupled to the compare circuit for receiving the compare signal, the control circuit providing a first control value corresponding to a first external device and the control circuit providing a plurality of internal control signals;

    a control register coupled to the control circuit for receiving the first control value, the control register selectively providing a first enable byte control value in response to the first control value; and

    a decode logic circuit coupled to the control register for receiving the first enable byte control value, coupled to the control circuit for receiving the plurality of internal control signals, and coupled to the central processing unit for receiving the plurality of address values, the decode logic circuit logically combining the first enable byte control value, a portion of the plurality of internal control signals, and a portion of the plurality of address values to provide a first enable byte signal in one of a second and a third logic state, wherein the first enable byte signal performs a write enable function when in the second logic state and the first enable byte signal performs a byte enable function when in the third logic state.

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