Data processing system for accessing an external device and method therefor

• US 5,724,604 A
• Filed: 08/02/1995
• Issued: 03/03/1998
• Est. Priority Date: 08/02/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moyer, William C.
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/510,510
• Time in Patent Office: 944 Days
• Field of Search: 395/800, 395/496, 395/559, 395/500, 395/494, 395/497.01, 395/490, 395/478, 395/479, 395/800.38, 395/800.43, 395/369, 395/310
• US Class Current: 712/43
• CPC Class Codes: G06F 12/0653 with centralised address assignment

Abstract

A data processing system (15) allows a user great flexibility in interfacing with a variety of memory devices (50, 55) and external peripheral devices (70, 72). In the data processing system, a control register (300, 400) is provided for dynamically controlling a function of a plurality of byte enable signals (204, 206, 208, 210) provided to any external device. In a first case, the register may indicate that the plurality of byte enable signals should function as a plurality of write enable signals. However, in a second instance, the register may indicate that the plurality of byte enable signals should function as a plurality of byte enable signals. The use of the register to determine a function of the byte enable signals allows a user greater functional flexibility without software intervention and without increasing a number of external integrated circuit pins required to select an external device.

Claims

1. A data processor, comprising:

a central processing unit for communicating a plurality of address values, a plurality of data values, and a plurality of control values; and

a system integration unit, the system integration unit, comprising;

a compare circuit coupled to the central processing unit for receiving the plurality of address values, the compare circuit providing a compare signal indicating an address range which includes a first one of the plurality of address values;

a control circuit coupled to the central processing unit for receiving the plurality of control values and coupled to the compare circuit for receiving the compare signal, the control circuit providing a first control value corresponding to a first external device and the control circuit providing a plurality of internal control signals;

a control register coupled to the control circuit for receiving the first control value, the control register selectively providing a first enable byte control value in response to the first control value; and

a decode logic circuit coupled to the control register for receiving the first enable byte control value, coupled to the control circuit for receiving the plurality of internal control signals, and coupled to the central processing unit for receiving the plurality of address values, the decode logic circuit logically combining the first enable byte control value, a portion of the plurality of internal control signals, and a portion of the plurality of address values to provide a first enable byte signal in one of a second and a third logic state, wherein the first enable byte signal performs a write enable function when in the second logic state and the first enable byte signal performs a byte enable function when in the third logic state.

2. The data processor of claim 1, further comprising:

an integrated circuit terminal coupled to the decode logic circuit for receiving the enable byte signal, the integrated circuit terminal providing the enable byte signal.

3. The data processor of claim 1, further comprising:

a plurality of control registers coupled to the control circuit for receiving the first control value, a first one of the plurality of control registers providing the first enable byte signal when the first control value is provided by the control circuit and a second one of the plurality of control registers providing a second enable byte signal when a second control value is provided by the control circuit.

4. The data processor of claim 3 wherein the second control value corresponds to a second external device.

5. The data processor of claim 3 wherein the plurality of control registers provide a plurality of enable byte signals to the decode logic circuit, the plurality of control registers providing each of the plurality of enable byte signals when a corresponding one of a plurality of control values is provided by the control circuit.

6. The data processor of claim 5 wherein each of the plurality of enable byte signals enable a preselected byte of data to be communicated by at least one of a plurality of external devices.

7. The data processor of claim 1 wherein the portion of the plurality of internal control signals comprises a size signal for indicating a size of a data value to be communicated in a data processing operation and a read signal for indicating whether the data value should be read or written during the data processing operation.

8. The data processor of claim 1 wherein the first enable byte signal performs the write enable function by enabling a selected external device when the central processing unit executes a write operation which accesses the selected external device.

9. The data processor of claim 8 wherein the first enable byte signal performs the write enable function by not enabling the selected external device when the central processing unit executes a read operation which accesses the selected external device.

10. The data processor of claim 1 wherein the first enable byte signal performs the byte enable function by enabling a selected external device when the central processing unit executes one of a read operation and a write operation.

11. The data processor of claim 10 wherein the first enable byte signal accesses one of an upper byte and a lower byte of the a first one of the plurality of data values when the central processing unit executes one of the read operation and the write operation.

12. The data processor of claim 10 wherein a chip select signal is asserted and provided to the selected external device.

13. The data processor of claim 12 wherein the first byte enable signal does not perform the byte enable function when the chip select signal is negated.

14. A data processing system, comprising:

a first external device which selectively communicates a first data value via a data bus;

a second external device which selectively communicates a second data value via the data bus; and

a data processor, comprising;

a central processing unit for communicating a plurality of internal address values, a plurality of internal data values, and a plurality of internal control values; and

a system integration unit, the system integration unit, comprising;

a compare circuit coupled to the central processing unit for receiving the plurality of internal address values, the compare circuit providing a first compare signal indicating an address range which includes a first one of the plurality of internal address values;

a control circuit coupled to the central processing unit for receiving the plurality of control values and coupled to the compare circuit for receiving the first compare signal, the control circuit providing a first control value corresponding to the first external device and the control circuit providing a first plurality of internal control signals;

a control register coupled to the control circuit for receiving the first control value, the control register selectively providing a first enable byte control value in response to the first control value;

a decode logic circuit coupled to the control register for receiving the first enable byte control value, coupled to the control circuit for receiving the plurality of internal control signals, and coupled to the central processing unit for receiving the plurality of internal address values, the decode logic circuit logically combining the first enable byte control value, a portion of the plurality of internal control signals, and a portion of the plurality of address values to provide a first enable byte signal in one of a second and a third logic state, wherein the first enable byte signal performs a write enable function for the first external device when in the second logic state and the first enable byte signal performs a byte enable function for the first external device when in the third logic state; and

a first integrated circuit terminal for providing the first enable byte signal to a first input of the first external device.

15. The data processing system of claim 14 wherein the control circuit provides a second control value corresponding to the second external device.

16. The data processing system of claim 15 wherein the control register is coupled to the control circuit for receiving the second control value and the control register selectively provides a second enable byte control value in response to the second control value.

17. The data processing system of claim 16 wherein the decode logic circuit logically combines the second enable byte control value, the portion of the plurality of internal control signals, and the portion of the plurality of address values to provide a second enable value in one of a fourth and a fifth logic state, wherein the second enable byte signal performs the write enable function when in the fourth logic state and performs the byte enable function when in the fifth logic state.

18. The data processing system of claim 17 wherein the second enable byte signal is provided to a second input of the first external device.

19. The data processing system of claim 18 wherein the first enable byte signal accesses a first portion of a data value stored in the first external device when in the third logic state and the second enable byte signal accesses a second portion of the data value stored in the first external device when in the fifth logic state.

20. A data processor, comprising:

a central processing unit for communicating a plurality of address values, a plurality of data values, and a plurality of control values;

a control circuit coupled to the central processing unit for receiving the plurality of control values, the control circuit providing a first control value and a plurality of internal control signals; and

a first control register coupled to the control circuit for receiving the first control value, the first control register selectively providing a first enable byte control value in response to the first control value, the first enable byte control value indicating when a first enable byte signal performs a write enable function and when the first enable byte signal performs a byte enable function.

21. The data processor of claim 20 wherein the first enable byte control value is a bit stored in the first control register.

22. The data processor of claim 20 wherein the first control register corresponds to a first external device.

23. The data processor of claim 22 wherein the control circuit provides a second control value in response to the plurality of control values.

24. The data processor of claim 23 further comprising:

a second control register coupled to the control circuit for receiving the second control value, the second control register selectively providing a second enable byte control value in response to the second control value, the second enable byte control value indicating when a second enable byte signal performs a write enable function and when the first enable byte signal performs a byte enable function.

25. The data processor of claim 24 wherein the second control register corresponds to a second external device.

26. A method for accessing an external device in a data processor, comprising the steps of:

communicating a plurality of address values, a plurality of data values, and a plurality of control values with a central processing unit;

coupling a compare circuit to the central processing unit for receiving the plurality of address values;

enabling the compare circuit to provide a compare signal indicating an address range which includes a first one of the plurality of address values;

coupling a control circuit to the central processing unit for receiving the plurality of control values;

coupling the control circuit to the compare circuit for receiving the compare signal;

enabling the control circuit to provide a first control value corresponding to a first external device and the control circuit providing a plurality of internal control signals;

coupling a control register to the control circuit for receiving the first control value;

enabling the control register to selectively provide a first enable byte control value in response to the first control value;

coupling a decode logic circuit to the control register for receiving the first enable byte control value;

coupling the decode logic circuit to the control circuit for receiving the plurality of internal control signals;

coupling the decode logic circuit to the central processing unit for receiving the plurality of address values; and

enabling the decode logic circuit to logically combine the first enable byte control value, a portion of the plurality of internal control signals, and a portion of the plurality of address values to provide a first enable byte signal in one of a second and a third logic state, wherein the first enable byte signal performs a write enable function when in the second logic state and the first enable byte signal performs a byte enable function when in the third logic state.

27. The method of claim 26, further comprising the steps of:

coupling a plurality of control registers to the control circuit for receiving the first control value;

enabling a first one of the plurality of control registers to provide the first enable byte signal when the first control value is provided by the control circuit; and

enabling a second one of the plurality of control registers to provide a second enable byte signal when a second control value is provided by the control circuit.

28. The method of claim 27 wherein the second control value corresponds to a second external device.

29. The method of claim 27 wherein the plurality of control registers provide a plurality of enable byte signals to the decode logic circuit and the plurality of control registers provides each of the plurality of enable byte signals when a corresponding one of a plurality of control values is provided by the control circuit.

30. The method of claim 29 wherein each of the plurality of enable byte signals enables a preselected byte of data to be communicated by at least one of a plurality of external devices.