Radio receiver with DC offset correction circuit

• US 5,724,653 A
• Filed: 12/20/1994
• Issued: 03/03/1998
• Est. Priority Date: 12/20/1994
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Davis, Paul Cooper, Baker, Thomas Wesley, Stetzler, Trudy Dawn, Petersen, Owe George, Lopata, Douglas D.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): TO, DORIS HA
• Application Number:
  US08/359,782
• Time in Patent Office: 1,169 Days
• Field of Search: 455/207, 455/209, 455/296, 455/324, 455/205, 455/278.1, 455/78, 455/214, 455/216, 455/303, 455/304, 455/310, 455/312, 455/337, 455/338, 455/314, 455/318, 375/319, 375/346, 375/349
• US Class Current: 455/296
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 25/064 Subtraction of the threshold from the signal, which is then compared to a supplementary fixed threshold

Abstract

The present invention relates to a radio receiver adapted for use in a time division multiple access (TDMA) system. The radio receiver includes DC compensator circuits configured to decrease the time required to cancel DC offset before received data bursts by DC coupling a radio frequency (RF) demodulator to a baseband channel. The radio receiver may also employ AC capacitive coupling having time modification so as to increase the AC coupled setting time and provide a low pole in a RF-to-Baseband interface.

Claims

1. A radio receiver comprising:

(a) an input adapted to receive an input radio signal;

(b) intermediate frequency (IF) means for generating an IF signal from said input radio signal;

(c) demodulation means coupled to said intermediate frequency means for demodulating said IF signal into an inphase (I) signal and a quadrature (Q) signal;

said demodulation means includes;

(i) first and second mixers for respectively providing said I and Q output signals from said IF signal;

(ii) first and second DC correction circuits respectively coupled to said first and second mixers and each respectively including a low pass filter, each said first and second DC correction circuits being adapted to respectively store a first DC offset of said first mixer and a second DC offset of said second mixer prior to reception of said input signal and to subtract said first and second DC offsets of said first and second mixers during reception of said input signal;

(d) switching means for periodically suspending application of said IF signal to said demodulation means, said DC correction circuits sampling said DC offsets during time intervals in which said IF signal is suspended;

wherein said low pass filter of each said DC correction circuit is configured to settle during said time intervals in which said IF signal is suspended, said intermediate frequency means includes a third mixer coupled between said input and said demodulation means and coupled to a local oscillator, and said switching means comprises a first switch coupled between said third mixer and said input and a second switch coupled between said local oscillator and said third mixer, said first and second switches periodically suspending application of said IF signal to said demodulation means.

2. A radio receiver as recited in claim 1, wherein said demodulation means further includes:

(iii) first and second amplifier means respectively coupled to said first and second DC correction circuits for amplifying the respective output I and Q signals of said first and second DC correction circuits.

3. A radio receiver as recited in claim 2, wherein said demodulation means further includes:

(iv) first and second analog-to-digital converters respectively coupled to said first and second amplifier means for converting the respective output signals of said first and second amplifier means to digital signals.

4. A radio receiver as recited in claim 3, wherein said input radio signal is received by an antenna and amplified by a low noise amplifier prior to being converted to said IF signal.

5. The radio receiver of claim 1, wherein a noise measurement is performed during suspension of said IF signal, thereby enabling errors in said DC offsets due to noise to be corrected.

6. The radio receiver of claim 1, wherein said input radio signal is periodically received during a predetermined time slot of a frame in a time division multiple access (TDMA) system.

7. A radio receiver comprising:

(a) a low noise amplifier for amplifying an input radio signal;

(b) intermediate frequency means coupled to said low noise amplifier for generating an intermediate frequency (IF) signal from said amplified input radio signal;

(c) demodulation means coupled to said intermediate frequency means for demodulating said IF signal into an inphase (I) signal and a quadrature (Q) signal;

said demodulation means including;

(i) first and second mixers for respectively providing said I and Q output signals from said IF signal;

(ii) first and second DC correction circuits respectively coupled to said first and second mixers and each respectively including a low pass filter, each said first and second DC correction circuits being adapted to respectively store a first DC offset of said first mixer and a second DC offset of said second mixer prior to reception of said input signal and to subtract said first and second DC offset signals of said first and second mixers during reception of said input signal;

(iii) first and second amplifier means respectively coupled to said first and second DC correction circuits for amplifying the respective output I and Q signals of said first and second DC correction circuits;

(iv) first and second analog-to-digital converters respectively coupled to said first and second amplifier means for converting the respective output signals of said first and second amplifiers to digital signals;

wherein said intermediate frequency means includes a third mixer coupled to both said low noise amplifier and a local oscillator, said intermediate frequency means further includes a first switch coupled intermediate said low noise amplifier and said third mixer and a second switch coupled intermediate said third mixer and said oscillator, whereby when said first and second switches are in an open position said low pass filter of each said first and second DC correction circuit is caused to settle.

8. A radio receiver as recited in claim 7, wherein said intermediate frequency means further includes an AC capacitor coupling the output signal of said third mixer to said demodulation means.

9. A radio receiver as recited in claim 8, wherein said radio receiver is a quadrature demodulating radio receiver.

10. A radio receiver comprising:

(a) a low noise amplifier for amplifying an input radio signal to provide an amplified input radio signal;

(b) intermediate frequency (IF) means for generating an IF signal from said amplified input radio signal;

(c) demodulation means coupled to said intermediate frequency means for demodulating said IF signal into an inphase (I) signal and a quadrature (Q) signal;

said demodulation means includes;

(i) first and second mixers for respectively providing said I and Q output signals from said IF signal;

(ii) first and second DC correction circuits respectively coupled to said first and second mixers and each respectively including a low pass filter, each said first and second DC correction circuits being adapted to respectively store a first DC offset of said first mixer and a second DC offset of said second mixer prior to reception of said input signal and to subtract said first and second DC offsets of said first and second mixers during reception of said input signal;

(d) switching means for periodically suspending application of said IF signal to said demodulation means, said DC correction circuits sampling said DC offsets during time intervals in which said IF signal is suspended;

wherein said low pass filter of each said DC correction circuit is configured to settle during said time intervals in which said IF signal is suspended, said intermediate frequency means includes a third mixer coupled between said low noise amplifier and said demodulation means and coupled to a local oscillator, and said switching means comprises a first switch coupled between said third mixer and said low noise amplifier and a second switch coupled between said local oscillator and said third mixer, said first and second switches periodically opening to suspend application of said IF signal to said demodulation means.