Method and apparatus for variable rate cardiac stimulation

• US 5,725,561 A
• Filed: 06/09/1995
• Issued: 03/10/1998
• Est. Priority Date: 06/09/1995
• Status: Expired due to Term

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Stroebel, John C., Markowitz, H. Toby, Hess, Michael F.
• Primary Examiner(s): Jastrzab, Jeffrey R.
• Application Number:
  US08/489,262
• Time in Patent Office: 1,005 Days
• Field of Search: 607/9, 607/17-19, 607/25
• US Class Current: 607/9
• CPC Class Codes: A61N 1/3622 comprising two or more electrodes co-operating with different heart regions
• CPC Class Codes: A61N 1/368 comprising more than one electrode co-operating with different heart regions A61N1/3622, A61N1/3627 take precedence

Abstract

A method and apparatus for variable rate cardiac stimulation, wherein sudden drops in the rate of delivery of stimulation pulses are avoided by means of rate smoothing and peak rate support functions. In one embodiment, circuitry in a cardiac pulse generator detects atrial events and maintains an updated value of the A-A time intervals between certain atrial events. If a preset ratio or total of these A-A intervals are found to have been shorter than the updated value by at a least a predetermined amount of time, a rate smoothing function is activated wherein the rate of delivery of stimulating pulses is prevented from changing, from cycle to cycle, by more than a predetermined maximum amount. A peak rate support function preferably employs the same updated value in the computation of "escape" intervals. Following the latest A-A interval, if that A-A interval is less than the updated value, then the updated value is used as the new escape interval. If the latest A-A interval is greater than or equal to the updated value but less than the previous updated value, the current escape interval is used as the new escape interval. If the latest A-A interval is less than both the previous updated value and the current updated value, the value updated is used as the new escape interval, and the pulse generator enters a decay mode wherein the escape interval is gradually and incrementally lengthened to prevent sudden changes in the rate of delivery of stimulation pulses.

Claims

1. A cardiac pulse delivery and sensing apparatus comprising:

a housing adapted to be implanted in an individual said housing containing means for generating and delivering stimulating pulses to an electrical connection outside said housing said electrical connection arranged and disposed for electrical connection to sensing and stimulating pulse delivery lead means and wherein said lead mean are configured and designed to allow for implantation so as to be in close association with said individual'"'"'s heart so as to provide electrical connection between said heart and said electrical connection,

a timing and control processor circuit and a memory circuit within said housing having control of the timing of delivery of said stimulating pulses and for timing said sensed heart signals and for storing values related to such timing in an associated portion of said memory circuit and wherein said processor circuit comprises as least two processors;

a rate smoothing determining processor for determining whether rate smoothing criteria are met in sensed signals from said heart when a rapid rate drop is detected and;

a rate support determining processor for determining from said values related to such timing when to maintain a support rate, said maintenance of support rate processor having two modes, a tracking mode which follows an intrinsic atrial rate and a decay mode which allows the support rate to fall in a controlled manner and wherein said timing and control processor circuit also comprises circuit means for adjusting the timing of said stimulating pulses in response to said rate smoothing processor and rate support processor'"'"'s determining.

2. An apparatus as set forth in claim 1 wherein said rate smoothing determining processor bases its determination on a current Averaged Atrial Interval (AAI) value stored and updated in said memory circuit in which value is the measure of a previous AAI summed with a value for an increment of time or decremented by a value for a decrement of time such that:

a) said previous AAI is incremented by a positive increment interval when the time between the last pair of atrial sensed events or the time between a leading sensed atrial event and a paced atrial event or the time between the last two atrial paced events is less than the value of the previous AAI, but

b) said previous AAI is decremented by a negative increment interval when the time between the last pair of atrial sensed events or the time between a leading sensed atrial event and a paced atrial event or the time between the last two atrial paced events is greater than the value of the previous AAI;

such that if the current AAI is less than the value of the previous AAI minus a predetermined Maximum Rate Drop interval value, then an indicator value in a memory circuit in favor of rate smoothing is "set".

3. An apparatus as set forth in claim 2 wherein when said indicator "Count N" is set in favor of rate smoothing and a next indicator value in said memory circuit will be either:

"set" depending on if the current AAI is less than the value of the previous AAI minus said predetermined Maximum Rate Drop interval value; and

"not-set" if not and wherein a set of all previously set or not-set indicator values is used by said rate smoothing determining circuit to determine whether or not to initiate rate smoothing.

4. An apparatus as set forth in claim 3 wherein the set of indicators available to be put into either said set or not-set condition is equal to a number P, said number P being a variable representing a number of memory circuit elements in said memory circuit that can be used for storing said set or not set variables and an index "CountP" is set equal to the variable from 1 to P that is being considered, and when the value of the index CountP=P, the next variable to be set or reset is indexed by CountP=1.

5. An apparatus as set forth in claim 2 wherein when said indicator is set a next indicator will be either:

"set" depending on if the current AAI is less than the value of the previous AAI minus said predetermined Maximum Rate Drop interval value; and

"not-set" if not and wherein the total of all previously set indicator values is determined and said total is compared by said rate smoothing determining circuit to a predetermined number N stored in said memory circuit and if said total is determined to be greater or equal to N, then said rate smoothing determining circuit signals said timing and control circuit to initiate rate smoothing.

6. An apparatus as set forth in claim 5 wherein the number N is predetermined by a user and stored by that user into said memory circuit for storing N'"'"'s value.

7. An apparatus as set forth in claim 2 wherein the rate smoothing is accomplished by said rate smoothing processor accomplishing the summing of the current AAI with a small additional increment to reach the next AAI.

8. An apparatus as set forth in claim 7 wherein said small additional increment size is a storable value set by a user and stored by that user into said memory circuit for storing said additional increment'"'"'s size value by use of a device that can communicate with said apparatus.

9. Apparatus as set forth in claim 1 wherein said timing and control processor circuit can be controlled by reference to a value by either said rate smoothing determining processor or by said rate support determining processor or by both processors depending on the value which is set by a user and stored by that user into said memory circuit.

10. Apparatus as set forth in claim 1 wherein said timing and control processor circuit is controlled by both said rate smoothing determining processor and by said rate support determining processor.

11. Apparatus as set forth in claim 9 wherein said rate support determining processor supports PRS and wherein said rate support processor is only activated upon achievement of a predetermined criterion.

12. Apparatus as set forth in claim 9 wherein said rate support determining processor supports PRS and wherein when said rate support processor is activated in accord with preset criteria, said activation causes an indication of said meeting of such criterion to be reported to the user.

13. A cardiac pulse delivery and sensing apparatus comprising:

a housing adapted to be implanted in an individual said housing containing means for generating and delivering stimulating pulses to an electrical connection outside said housing said electrical connection arranged and disposed for electrical connection to sensing and pulse delivery leads connected thereto and wherein said leads are configured and designed to allow for implantation so as to be in close association with said individual'"'"'s heart so as to provide electrical connection between said heart and said electrical connection,

a timing and control processor circuit and a memory circuit within said housing having control of the timing of delivery of said stimulating pulses and for timing said sensed heart signals and for storing values related to such timing in an associated portion of said memory circuit wherein said processor circuit comprises;

a rate smoothing determining processor for determining whether rate smoothing criteria are met in sensed signals from said heart if a rapid rate drop is detected; and

wherein said processor circuit also comprises circuit means for adjusting the timing of said stimulating pulses in response to said determination so as to allow said drop to occur in a smoothed manner without first raising a pacing rate to a predetermined rate.

14. A cardiac pulse delivery and sensing apparatus comprising:

a housing adapted to be implanted in an individual said housing containing means for generating and delivering stimulating pulses to an electrical connection outside said housing said electrical connection arranged and disposed for electrical connection to sensing and pulse delivery leads connected thereto and wherein said lead are configured and designed to allow for implantation so as to be in close association with said individual'"'"'s heart so as to provide electrical connection between said heart and said electrical connection,

a timing and control processor circuit and a memory circuit means within said housing having control of the timing of delivery of said stimulating pulses, for timing said sensed heart signals and for storing values related to such timing in an associated portion of said memory circuit means and wherein said processor circuit comprises;

a rate support determining processor for determining from said stored values when to maintain a support rate so as to prevent rapid rate drops; and

wherein said processor circuit also comprises circuit means for adjusting the timing of said stimulating pulses in response to said determination, said support rate processor having two modes, a tracking mode which follows an intrinsic atrial rate and a decay mode which allows the support rate to fall in a controlled manner.

15. Apparatus as set forth in claim 14, said timing and control circuit further comprising a sensor and a rate drop determination circuit, wherein the rate support determining processor is only triggered by said sensor and rate drop determination circuit and wherein said rate drop determination circuit determines based on sensed depolarizations that an occurrence of a drop in intrinsic rate from a predetermined maximum to a predetermined minimum within a given period has occurred.

16. Apparatus as set forth in claim 14, said timing and control circuit further comprising a sensor and a rate drop determination circuit, wherein the rate support determining processor is only triggered by said sensor and rate drop determination circuit that determines based on sensed depolarizations that an occurrence of a drop in intrinsic rate by a predetermined absolute value over a given time period has occurred.

17. Apparatus as set forth in claim 14, said timing and control circuit further comprising a sensor and a rate drop determination circuit, wherein the rate support determining processor is triggered by triggered by said sensor and rate drop determination circuit that determines based on sensed depolarizations that an occurrence of a predefined drop in the intrinsic rate over a given period has occurred.

18. Apparatus as set forth in claim 14 wherein said timing and control circuit retains timing values of escape intervals, including a present and a previous escape interval, and wherein when the rate support determining processor is on, said timing and control circuit functions by increasing an escape interval to slow pacing from one paced beat to the next, but does not function to slow pacing during "decay beats" while in said decay mode, the number of said decay beats being determined by whether an intrinsic event is found within said previous escape interval.

19. A method for timing and controlling the delivery of pacing pulses to a heart comprising one step from the following set of steps, a, b, and c:

a)

     1) monitoring and detecting occurrences of rapid rate drop

2) when a rapid heart rate is detected, enabling a processor to apply smoothing criteria to the timing of delivery of subsequent pacing pulses,

b)

     1) monitoring and detecting occurrences of wide variation in heart rate,

2) enabling a processor to apply rate support criteria to subsequent pacing pulses following the detection of an occurrence of wide rate variation, and

c)

     1) monitoring and detecting occurrences of rapid rate drop and wide variation in intrinsic heart rate

2) when a rapid heart rate drop or occurrence of wide rate variation is detected, enabling a processor to apply a combination of rate support and rate smoothing criteria to the timing and delivery of subsequent pacing pulses.

20. A method for timing and controlling the delivery of pacing pulses to a heart comprising:

monitoring and detecting occurrences of rapid rate drop when an intrinsic rapid heart rate drop is detected, enabling a processor to apply smoothing criteria to the timing of delivery of subsequent pacing pulses such that an intrinsic rapid rate drop is not allowed to occur but instead a smoothed rate drop is supported by said timing.

21. A method for timing and controlling the delivery of pacing pulses to a heart comprising:

monitoring and detecting occurrences of wide variation in heart rate when an occurrence of wide variation in heart rate is detected, enabling a processor to apply rate support criteria to the timing of delivery of subsequent pacing pulses such that the paced patient'"'"'s intrinsic rate is not allowed to fall by adjusting the timing of pacing pulse delivery downward no faster than extinction of a timed interval adjusted by said processor to reflect the amount of rate support needed so said interval is directly proportional in size to the amount of support determined by said processor to be needed.