Process for micromechanical fabrication

• US 5,725,729 A
• Filed: 08/15/1996
• Issued: 03/10/1998
• Est. Priority Date: 09/26/1994
• Status: Expired due to Term

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Greiff, Paul
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US08/698,479
• Time in Patent Office: 572 Days
• Field of Search: 216/2, 216/11, 437/228, 437/921, 437/901, 148/DIG. 159, 156/628, 156/630, 156/655, 156/657
• US Class Current: 438/50
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/0019 Flexible or deformable structures not provided for in groups B81C1/00142 - B81C1/00182
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends
• CPC Class Codes: G01P 2015/0831 the mass being of the paddle type having the pivot axis between the longitudinal ends of the mass, e.g. see-saw configuration

Abstract

An improved process for fabricating micromechanical devices having movable members, such as gyros and accelerometers. A starting wafer includes an oxidized silicon wafer which has been wafer bonded to a second silicon wafer which has a thin N layer on a P substrate. The wafer is patterned, doped and etched in a series of process steps which include the deposition of epitaxial layers to configure critical device dimensions and geometry. Metallizations are deposited for electrical/electronic interconnections. The process includes an ability to integrate on-chip electronics on the silicon substrate. Alignment difficulties and thermal mismatch associated with prior art processes are minimized.

Claims

1. A process for fabricating a micromachined structure, said process comprising the steps of:

selecting a starting wafer having a first single crystal silicon substrate with at least one dielectric surface and a second single crystal silicon substrate bonded to said at least one dielectric surface of said first silicon substrate;

masking, patterning and diffusing said second single crystal silicon substrate with a first impurity in selected regions forming at least one of an electrode region and an anchor region;

depositing a first sacrificial layer of single crystal silicon over said at least one of said electrode region and said anchor region, forming a gap spacer;

depositing a first device layer of single crystal silicon over said gap spacer, said first device layer being doped in selected areas with an impurity to impart etch resistance to form a first device layer that has etch resistant areas;

masking and patterning said first device layer forming a suitable geometry for said micromachined structure; and

etching away said first sacrificial layer of single crystal silicon leaving said micromachined structure while preserving said dielectric surface.

2. The process of claim 1 further including the step of adding metallizations for bonding pads and interconnects for electrical interconnection with said electrode region.

3. The process of claim 1 wherein said at least one dielectric surface is a silicon nitride surface.

4. The process of claim 1 wherein said at least one dielectric surface is an oxide surface.

5. The process of claim 1 wherein said first impurity is boron.

6. The process of claim 1 further including a step of removing selected portions of said first sacrificial layer to form vias therein as anchor locations.

7. The process of claim 1 wherein said first device layer is a P+boron doped epitaxial layer.

8. The process of claim 1 wherein said etch resistant impurity includes at least one of Germanium and Boron.

9. The process of claim 1 wherein said micromachined structure patterned in said first device layer includes a membrane for use as a pressure sensor.

10. The process of claim 1 further including the steps of depositing a second sacrificial layer of single crystal silicon over said first device layer and depositing a second device layer of single crystal silicon over said second sacrificial layer, and wherein said first device layer comprises a bottom of a hollow beam and said second device layer comprises a top and sides of said beam.

11. The process of claim 1 wherein said micromachined structure patterned in said first device layer includes a see-saw accelerometer and a plurality of linkages.

12. The process of claim 1 further including the step of etching away selected portions of said second silicon substrate and said first device layer.

13. The process of claim 1 wherein said etch resistant impurity is at least one of arsenic and phosphorous and said first sacrificial layer is etched away by electrochemical etching.

14. The process of claim 12 wherein selected portions of said second silicon substrate and said first device layer are etched away by electrochemical etching.

15. The process of claim 1 wherein said micromachined structure patterned in said first device layer includes at least portions of a gyroscope and a plurality of linkages.

16. The process of claim 1 further including the steps of doping said first silicon substrate to form electrodes and aligning said first silicon substrate with said second silicon substrate.

17. The process of claim 16 wherein said first silicon substrate is doped to form a silicon z bar and said micromachined structure fabricated according to said process is a double gimbal gyroscope.

18. The process of claim 1 wherein said electrode regions are anchored to said dielectric surface by said diffusing step.

19. The process of claim 1 wherein said step of etching is performed using EDP etching.