Method of repairing defective traces in an integrated circuit structure

• US 5,725,995 A
• Filed: 06/07/1995
• Issued: 03/10/1998
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Duda, Kathleen
• Application Number:
  US08/486,521
• Time in Patent Office: 1,007 Days
• Field of Search: 430/311, 430/315, 430/324, 430/396, 250/492.2, 250/492.3, 427/523, 427/526
• US Class Current: 430/315
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Claims

1. A method of repairing defective traces in an integrated circuit structure comprising the steps of:

using a plurality of probe points to probe a trace location and a test location to test electrical continuity between said trace location and a test location;

determining that a trace is formed with a defective portion; and

depositing metal over the defective portion of said trace.

2. The method of claim 1, wherein prior to the step of depositing metal over the defective portion, the method further comprises the step of patterning a resist layer.

3. The method of claim 2, wherein said resist is patterned with an exposure source selected from the group consisting of ion-beam, electron-beam, and optical.

4. The method of claim 2, wherein the metal is deposited through openings in the patterned resist layer.

5. The method of claim 1, wherein the metal is deposited over the defective portion of said trace by an ion-beam.

6. The method of claim 1, wherein the integrated circuit structure is tested for defective traces at the integrated circuit logic unit level.

7. The method of claim 1, wherein the step of probing a trace location comprises locating said trace through the use of a database in which defect locations for the circuit are represented.

8. The method of claim 1, wherein a pattern of probe points is used to probe a trace location.