Active matrix substrate and switching element

• US 5,726,461 A
• Filed: 01/02/1996
• Issued: 03/10/1998
• Est. Priority Date: 01/31/1995
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Hirakawa, Kazuko, Shimada, Takayuki, Ban, Atsushi
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/581,965
• Time in Patent Office: 798 Days
• Field of Search: 257/746, 257/59, 257/72, 257/88, 257/89, 257/90, 257/91, 257/92, 257/93
• US Class Current: 257/59
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An active matrix substrate comprises an insulation substrate, a plurality of pixel electrodes arranged in a matrix form on the insulation substrate, a switching element provided for each of the pixel electrodes, gate signal lines for supplying a signal to the switching elements, and source signal lines for supplying a data signal to the pixel electrodes via the corresponding switching elements. Each switching element is a thin film transistor (TFT) including a gate electrode, an insulating layer formed on the insulation substrate to cover the gate electrode, a semiconductor layer formed on the insulating layer opposite to the gate electrode, a source electrode formed on one end of the semiconductor layer, one of the source signal lines overlapping the source electrode, and a drain electrode formed on the other end of the semiconductor layer, one of the gate signal lines overlapping the drain electrode. The source and drain electrodes have a two-layer structure of an upper amorphous semiconductor layer and a lower micro-crystalline semiconductor layer. The source signal lines have a two-layer structure of an upper conductive layer and a lower protection layer.

Claims

1. An active matrix substrate comprising:

an insulation substrate;

a plurality of pixel electrodes arranged in a matrix form on the insulation substrate;

a switching element provided for each of the pixel electrodes;

gate signal lines for supplying to the switching elements a signal for controlling an electrically conducting state and a non-conducting state of the switching elements; and

source signal lines for supplying a data signal to the pixel electrodes via the corresponding switching elements;

wherein each switching element is a thin film transistor (TFT) including;

a gate electrode formed on the insulation substrate;

an insulating layer formed on the insulation substrate so as to cover the gate electrode;

a semiconductor layer formed on the insulating layer in a portion opposite to one of the gate electrodes, the semiconductor layer including a channel region;

a source electrode formed on one end of the semiconductor layer, one of the source signal lines overlapping the source electrode; and

a drain electrode formed on the other end of the semiconductor layer, one of the pixel electrodes overlapping the drain electrode,

and wherein the source and drain electrodes have a two-layer structure of an upper amorphous semiconductor layer and a lower micro-crystalline semiconductor layer.

2. An active matrix substrate according to claim 1, wherein the source and drain electrodes are made of an n-type silicon and have a two-layer structure of an upper amorphous n-type silicon layer and a lower micro-crystalline n-type silicon layer.

3. An active matrix substrate according to claim 1, wherein the TFT is of a channel etch type.

4. An active matrix substrate according to claim 1, wherein the TFT further includes a second insulating layer formed on the channel region of the semiconductor layer so as to protect the channel region, the TFT being of a reverse stagger type.

5. An active matrix substrate according to claim 1, wherein each of the source signal lines has a two-layer structure of an upper conductive layer and a lower protection layer made of an insulator.

6. An active matrix substrate according to claim 4, wherein each of the source signal lines has a two-layer structure of an upper conductive layer and a lower protection layer which is patterned from a same insulating layer as the second insulating layer.

7. An active matrix substrate according to claim 1, wherein each of the source signal lines has a two-layer structure of an upper conductive layer and a lower protection layer made of a semiconductor.

8. An active matrix substrate according to claim 7, wherein the lower protection layer is patterned from a same layer as the semiconductor layer formed on the insulating layer on the gate electrode.

9. An active matrix substrate according to claim 7, wherein the lower protection layer is an amorphous semiconductor layer.

10. An active matrix substrate according to claim 7, wherein the lower protection layer has a two-layer structure of an upper micro-crystalline semiconductor layer and a lower amorphous semiconductor layer.

11. An active matrix substrate according to claim 7, wherein the lower protection layer has a three-layer structure of an upper amorphous semiconductor layer, a middle micro-crystalline semiconductor layer, and a lower amorphous semiconductor layer.

12. An active matrix substrate according to claim 10, wherein

the lower amorphous semiconductor layer of the lower protection layer is patterned from a same semiconductor layer as the semiconductor layer formed on the insulating layer on the gate electrode, and

the upper micro-crystalline semiconductor layer of the lower protection layer is patterned from a same micro-crystalline semiconductor layer as the lower micro-crystalline layer of the source and drain electrodes.

13. An active matrix substrate according to claim 11, wherein

the lower amorphous semiconductor layer of the lower protection layer is patterned from a same semiconductor layer as the semiconductor layer formed on the insulating layer on the gate electrode,

the middle micro-crystalline semiconductor layer of the lower protection layer is patterned from a same micro-crystalline semiconductor layer as the lower micro-crystalline layer of the source and drain electrodes, and

the upper amorphous semiconductor layer of the lower protection layer is patterned from a same amorphous semiconductor layer as the upper amorphous semiconductor layer of the source and drain electrodes.

14. An active matrix substrate according to claim 1, wherein the source signal lines and the pixel electrodes are patterned from a same conductive thin film.

15. An active matrix substrate according to claim 1, wherein each of the source signal lines has an upper conductive layer and a lower protection layer which is provided at crossings of the source signal lines over the gate signal lines.

16. An active matrix substrate according to claim 15, wherein the lower protection layer is made of an amorphous semiconductor.

17. An active matrix substrate according to claim 15, wherein the lower protection layer has a two-layer structure of an upper micro-crystalline semiconductor layer and a lower amorphous semiconductor layer.

18. An active matrix substrate according to claim 15, wherein the lower protection layer has a three-layer structure of an upper amorphous semiconductor layer, a middle micro-crystalline semiconductor layer, and a lower amorphous semiconductor layer.

19. A thin film transistor (TFT) used as a switching element for an active matrix substrate, comprising:

a gate electrode formed on an insulation substrate;

an insulating layer formed on the gate electrode;

a semiconductor layer formed on the insulating layer including a channel region;

a source electrode formed on one end of the semiconductor layer, a first conductive layer overlapping the source electrode; and

a drain electrode formed on the other end of the semiconductor layer, a second conductive layer overlapping the drain electrode,

wherein the source and drain electrodes have a two-layer structure of an upper amorphous semiconductor layer and a lower micro-crystalline semiconductor layer.

20. A TFT according to claim 19, wherein the source and drain electrodes are made of an n-type silicon and have a two-layer structure of an upper amorphous n-type silicon layer and a lower micro-crystalline n-type silicon layer.