Silicon carbide MOSFET having self-aligned gate structure

• US 5,726,463 A
• Filed: 08/07/1992
• Issued: 03/10/1998
• Est. Priority Date: 08/07/1992
• Status: Expired due to Fees

• Current Assignee: General Electric Company, Wolfspeed, Inc.
• Original Assignee: General Electric Company
• Inventors: Edmond, John Adam, Brown, Dale Marius, Saia, Richard Joseph, Palmour, John Williams
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): Wallace, Valencia Martin
• Application Number:
  US07/925,823
• Time in Patent Office: 2,041 Days
• Field of Search: 257/76, 257/77, 257/288, 257/330, 257/331, 257/332, 257/333
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

A SiC MOSFET having a self-aligned gate structure is fabricated upon a monocrystalline substrate layer, such as a p type conductivity α6H silicon carbide (SiC) substrate. An SiC n+ type conductivity layer, epitaxially grown on the substrate layer, includes a steep-walled groove etched through the n+ SiC layer and partially into the p SiC layer. The groove is lined with a thin layer of silicon dioxide which extends onto the n+ type conductivity layer. A filling of gate metal over the layer of silicon dioxide is contained entirely in the groove. The silicon dioxide layer includes a first window extending to the filling of gate metal in the groove, and second and third windows extending to the n+ type conductivity layer on either side of the groove, respectively. A gate contact extends through the first window to the filling of gate metal in the groove while drain and source contacts extend through the second and third window, respectively, to make contact with the n+ type conductivity layer in drain and source regions on either side of the groove.

Claims

1. A metal oxide semiconductor device having a self-aligned gate structure comprising:

a first silicon carbide layer of a first conductivity type;

a second silicon carbide layer of a second conductivity type, opposite to said first conductivity type and epitaxially deposited upon said first silicon carbide layer;

a gate groove extending through said second layer and partially into said first layer;

a first insulating layer atop said second silicon carbide layer and lining the walls and bottom of said groove;

a filling of conductive material contained entirely in said groove so as to cover said first insulating layer in said groove;

a second insulating layer atop the portion of said first insulating layer not covered by said conductive material, said second insulating layer extending over said conductive material;

a plurality of windows in said first and second insulating layers including a first window extending through said second insulating layer to said filling of conductive material in said groove and second and third windows extending through said first and second insulating layers to said second silicon carbide layer on either side of said groove, respectively, the second silicon carbide layer constituting a source region on one side of said groove and constituting a drain region on the other side of said groove; and

conductive means extending through each of said windows to make contact with said filling of conductive material so as to form a gate electrode and to make contact with said second silicon carbide layer on either side of said groove so as to form a source electrode and a drain electrode, respectively.

2. The apparatus of claim 1 wherein each of said first and second insulating layers comprises silicon dioxide.

3. The apparatus of claim 1 wherein the gate electrode has edges that are substantially aligned with edges of the source region and the drain region so as to minimize any overlap of the silicon carbide layers by the gate electrode walls.

4. The apparatus of claim 2 wherein the gate electrode has edges that are substantially aligned with edges of the source region and the drain region so as to minimize any overlap of the silicon carbide layers by the gate electrode walls.

5. The metal oxide semiconductor device of claim 2 wherein said first silicon carbide layer is of p type conductivity including a dopant selected from the group consisting of aluminum and boron at a dopant concentration of 10¹⁴ -10¹⁶ centimeters^-3 and said second silicon carbide layer is of n type conductivity at a dopant concentration of 10¹⁸ -10²⁰ centimeters^-3.